Z8F082ASJ020EG Datasheet, PDF (196/282 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F082A Series
Product Specification
179
Table 107. NVDS Read Time
Operation
Read (16 byte array)
Read (64 byte array)
Read (128 byte array)
Write (16 byte array)
Write (64 byte array)
Write (128 byte array)
Illegal Read
Illegal Write
Minimum
Latency
875
876
883
4973
4971
4984
43
31
Maximum
Latency
9961
8952
7609
5009
5013
5023
43
31
If NVDS read performance is critical to your software architecture, you can optimize your
code for speed. Try the first suggestion below before attempting the second.
1. Periodically refresh all addresses that are used. The optimal use of NVDS in terms of
speed is to rotate the writes evenly among all addresses planned to use, bringing all
reads closer to the minimum read time. Because the minimum read time is much less
than the write time, however, actual speed benefits are not always realized.
2. Use as few unique addresses as possible to optimize the impact of refreshing, plus
minimize the requirement for it.
PS022827-1212
PRELIMINARY
NVDS Code Interface