Z89135 Datasheet, PDF (58/66 Pages) Zilog, Inc. – Low-Cost DTAD Controller

Z89135/136 (ROMless)
Low-Cost DTAD Controller
Z8 CONTROL REGISTERS (Continued)
Zilog
R246 P2M
D7 D6 D5 D4 D3 D2 D1 D0
* Default Setting After Reset
P20 - P27 I/O Definition
0 Defines Bit as Output
1 Defines Bit as Input *
Figure 70. Port 2 Mode Register
(F6H: Write Only)
R247 P3M
D7 D6 D5 D4 D3 D2 D1 D0
* Default Setting After Reset
0 Port 2 Pull-Ups Open Drain *
1 Port 2 Pull-Ups Active
0 P31, P32 Digital Mode *
1 P31, P32 Analog Mode
0 P32 = Input *
P35 = Output *
1 P32 = /DAV0/RDY0
P35 = RDY0//DAV0
00 P33 = Input *
P34 = Output *
01 P33 = Input
P34 = /DM
10 P33 = Input
P34 = /DM
11 P33 = /DAV1/RDY1
P34 = RDY1//DAV1
0 P31 = Input (TIN) *
P36 = Output (TOUT) *
1 P31 = /DAV2/RDY2
P36 = RDY2//DAV2
0 P30 = Input
P37 = Output
Reserved
Figure 71. Port 3 Mode Register
(F7H: Write Only)
R248 P01M
D7 D6 D5 D4 D3 D2 D1 D0
* Default Setting After Reset
P00 - P03 Mode
00 Output
01 Input *
1X A11 - A8
Stack Selection
0 External
1 Internal *
P10 - P17 Mode
00 Byte Output
01 Byte Input *
10 AD7 - AD0
11 High-Impedance AD7 - AD0,
/AS, /DS, /R//W, A11 - A8,
A15 - A12, If Selected
External Memory Timing
0 Normal *
1 Extended
P04 - P07 Mode
00 Output
01 Input *
1X A15 - A12
Figure 72. Port 0 Mode Register
(F8H: Write Only)
R249 IPR
D7 D6 D5 D4 D3 D2 D1 D0
Interrupt Group Priority
000 Reserved
001 C > A > B
010 A > B > C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
IRQ1, IRQ4 Priority (Group C)
0 IRQ1 > IRQ4
1 IRQ4 > IRQ1
IRQ0, IRQ2 Priority (Group B)
0 IRQ2 > IRQ0
1 IRQ0 > IRQ2
IRQ3, IRQ5 Priority (Group A)
0 IRQ5 > IRQ3
1 IRQ3 > IRQ5
Reserved
Figure 73. Interrupt Priority Register
(F9H: Write Only)
1-58
PRELIMINARY
DS97TAD0300