Z89135 Datasheet, PDF (48/66 Pages) Zilog, Inc. – Low-Cost DTAD Controller

Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
Z8_IRQ3. This bit can be read from both Z8 and DSP and
can be set by DSP only. Addressing this location accesses
bit D3 of the Z8 IRQ register, hence this bit is not imple-
mented in the ICR. During the interrupt service routine ex-
ecuted on the Z8 side, the User has to reset the Z8_IRQ3
bit by writing a 1 to bit D0 of the DSPCON. The hardware
of the Z89165/C66 automatically resets Z8_IRQ3 bit three
instructions of the Z8 after 1 is written to its location in reg-
ister bank 0F. This delay provides the timing synchroniza-
tion between the Z8 and the DSP sides during interrupts.
In summary, the interrupt service routine of the Z8 for IRQ3
should be finished by:
DSP Enable_INT. Writing a 1 to this location enables glo-
bal interrupts of the DSP while writing 0 disables them. A
system Reset globally disables all interrupts.
DSP_IPRX. This three-bit group defines the Interrupt Se-
lection logic according to Table 14.
Clear_IRQX. These bits can be accessed by the DSP
only. Writing a 1 to these locations rests the corresponding
DSP_IRQX bits to 0. Clear_IRQX are virtual bits and are
not implemented.
LD
OR
POP
IRET
;RP,#%0F
;r12,#%01
;RP
;
DSP_IPR[2-0]
210
000
001
010
011
100
101
110
111
Table 14. DSP Interrupt Selection
Z8_INT is
switched to
INT2
INT1
INT2
INT1
INT0
INT0
Reserved
Reserved
A/D_INT is
switched to
INT1
INT2
INT0
INT0
INT2
INT1
Reserved
Reserved
D/A_INT is
switched to
INT0
INT0
INT1
INT2
INT1
INT2
Reserved
Reserved
DSP ANALOG DATA REGISTERS
The D/A conversion is DSP driven by sending 10-bit data
to the EXT5 of the DSP. The six remaining bits of EXT5 are
not used (Figure 34).
A/D supplies 8-bit data to the DSP through the register
EXT5 of the DSP. From the 16 bits of EXT5, only bits 2
through 9 are used by the A/D (Figure 35). Bits 0 and 1 are
padded with zeroes
F E D CBA9 8 7 6 5 4 3 2 1 0
10-Bit Data for D/A
(Write Only)
Reserved
Figure 34. EXT5 Regoster D/A Mode Definition
1-48
F EDCBA9 8 7 6 5 4 3 2 1 0
Reserved
8-Bit Data From A/D Converter
(Read Only)
Reserved
Figure 35. EXT5 Register A/D Mode Definition
PRELIMINARY
DS97TAD0300