Z89135 Datasheet, PDF (3/66 Pages) Zilog, Inc. – Low-Cost DTAD Controller

Zilog
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Z8 Core Processor
DSP Coprocessor
The Z8 is Zilog’s 8-bit MCU core with an Expanded Regis- The DSP coprocessor is a second generation, 16-bit two’s
1 ^{ter File to allow access to register-mapped peripheral and complement CMOS Digital Signal Processor (DSP). Most}
I/O circuits. The Z8^® MCU offers a flexible I/O scheme, an instructions, including multiply and accumulate, are ac-
efficient register and address space structure, and a num- complished in a single clock cycle. The processor contains
ber of ancillary features.
two on-chip data RAM blocks of 256 words, a 6K word pro-
gram ROM, 24-bit ALU, 16 x 16 multiplier, 24-bit Accumu-
For applications demanding powerful I/O capabilities, the _{lator, shifter, six-level stack, three vectored interrupts, and}
Z89135/136 offers 47 pins dedicated to input and output. _{two inputs for conditional program jumps. Each RAM block}
These lines are grouped into six ports. Each port is config- _{contains a set of four pointers which may be incremented}
urable under software control to provide timing, status sig- _{or decremented automatically to affect hardware looping}
nals and parallel I/O with or without handshake.
without software overhead. The data RAMs can be simul-
There are four basic memory resources for the Z8 that are
available to support a wide range of configurations: Pro-
taneously addressed and loaded to the multiplier for a true
single cycle scalar multiply.
gram Memory, Register File, Data Memory, and Expanded _{Four external DSP registers are mapped into the expand-}
Register File. The Z8 core processor is characterized by _{ed register file of the Z8. Communication between the Z8}
an efficient register file that allows any of 256 on-board _{and the DSP occurs through those common registers}
data and control registers to be the source and/or the des- _{which form the mailbox registers.}
tination of almost any instruction. Traditional microproces-
sor accumulator bottlenecks are eliminated.
The analog signal is generated by a 10-bit resolution Pulse
Width Modulator. The PWM output is a digital signal with
The Register File is composed of 236 bytes of general-pur- _{CMOS output levels. The output signal has a resolution of}
pose registers, four I/O port register,s and 15 control and _{1 in 1024 with a sampling rate of 16 kHz (XTAL = 20.48}
status registers. The Expanded Register File consists of _{MHz). The sampling rate can be changed under software}
mailbox registers, WDT mode register, DSP Control regis- _{control and can be set at 4, 10, 16, and 64 kHz. The dy-}
ter, Stop-Mode Recovery register, Port Configuration reg- _{namic range of the PWM is from 0 to 4V.}
ister, and the control and data registers for Port 4 and Port
5.
An 8-bit resolution half-flash A/D converter is provided.
The conversion is conducted with a sampling frequency of
To unburden the software from supporting the real-time _{8, 16, 32, 64, or 128 kHz. (XTAL = 20.48 MHz) in order to}
problems, such as counting/timing and data communica- _{provide oversampling. The input signal is 4V peak to peak.}
tion, the Z8 offers two on-chip counter/timers with a large _{Scaling is normally ±1.25V for the 2.5V peak to peak off-}
number of user selectable modes.
set.
Watch-Dog Timer and Stop-Mode Recovery features are
software driven by setting specific bits in control registers.
STOP and HALT instructions support reduced power op-
eration. The low power STOP Mode allows parameter in-
formation to be stored in the register file if power fails. An
external capacitor or battery retains power to the device.
Two additional timers (Timer2 and Timer3) have been
added to support different sampling rates for the A/D and
D/A converters. These timers are free running counters
that divide the crystal frequency to the appropriate sam-
pling of frequency.
Notes: All signals with a preceding front slash, "/", are ac-
tive Low. For example, B//W (WORD is active Low); /B/W
(BYTE is active Low, only).
Power connections follow conventional descriptions be-
low:
Connection
Power
Ground
Circuit
V_CC
GND
Device
V_DD
V_SS
DS97TAD0300
PRELIMINARY
1-3