Z89135 Datasheet, PDF (37/66 Pages) Zilog, Inc. – Low-Cost DTAD Controller

Zilog
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Power-On Reset (POR). A timer circuit clocked by a ded- STOP. This instruction turns off the internal clock and ex-
icated on-board RC oscillator is used for the Power-On Re- ternal crystal oscillation. It reduces the standby current to
set (POR) timer function. The POR time allows V_CC and
the oscillator circuit to stabilize before instruction execu-
300 µA or less. The STOP Mode is terminated by a reset
only, either by WDT time-out, POR, SMR recovery or ex-
1
tion begins.
ternal reset. This causes the processor to restart the appli-
cation program at address 000CH. In order to enter STOP
The POR timer circuit is a one-shot timer triggered by one _{(or HALT) Mode, it is necessary to first flush the instruction}
of three conditions:
pipeline to avoid suspending execution in mid-instruction.
s Power fail to Power OK status
To do this, the user must execute a NOP (opcode=FFH)
immediately before the appropriate sleep instruction, for
s Stop-Mode Recovery (if D5 of SMR=1)
example:
s WDT time-out.
FF
6F
The POR time is a nominal 5 ms. Bit 5 of the Stop-Mode FF
Register determines whether the POR timer is bypassed _7F
after Stop-Mode Recovery (typical for external clock,
RC/LC oscillators).
NOP
STOP
NOP
HALT
;clear the pipeline
;enter STOP Mode
or
;clear the pipeline
;enter HALT Mode
HALT. HALT turns off the internal CPU clock, but not the
XTAL oscillation. The counter/timers and external inter-
rupts IRQ0, IRQ1, IRQ2, and IRQ3 remain active. The de-
vices are recovered by interrupts, either externally or inter-
nally generated.
DS97TAD0300
PRELIMINARY
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