Z89135 Datasheet, PDF (21/66 Pages) Zilog, Inc. – Low-Cost DTAD Controller

Zilog
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Port 0. (P07-P00). Port 0 is an 8-bit, bidirectional, CMOS- ble) depending on the required address space. If the ad-
compatible port. These eight I/O lines are configured un- dress range requires 12 bits or less, the upper nibble of
1 ^{der software control as a nibble I/O port, or as an address Port 0 can be programmed independently as I/O while the}
port for interfacing external memory. The input buffers are lower nibble is used for addressing. If one or both nibbles
Schmitt-triggered and the output drivers are push-pull. are needed for I/O operation, they are configured by writ-
Port 0 is placed under handshake control. In this configu- ing to the Port 0 mode register.
ration, Port 3, lines P32 and P35 are used as the hand-
shake control /DAV0 and RDY0. Handshake signal direc- ^{In ROMless mode, after a hardware reset, Port 0 is config-}
tion is dictated by the I/O direction to Port 0 of the upper ^{ured as address lines A15-A8, and extended timing is set}
nibble P07-P04. The lower nibble must have the same di- ^{to accommodate slow memory access. The initialization}
rection as the upper nibble.
routine can include reconfiguration to eliminate this ex-
tended timing mode. (In ROM mode, Port 0 is defined as
The Auto Latch on Port 0 puts valid CMOS levels on all input after reset.)
CMOS inputs which are not externally driven. Whether this
level is 0 or 1, cannot be determined. A valid CMOS level, ^{Port 0 is set in the high-impedance mode if selected as an}
rather than a floating node, reduces excessive supply cur- ^{address output state along with Port 1 and the control sig-}
rent flow in the input buffer.
nals /AS, /DS and R//W (Figure 10).
For external memory references, Port 0 provides address
bits A11-A8 (lower nibble) or A15-A8 (lower and upper nib-
4
Z89135/136
MCU
4
Port 0
(I/O or A15 - A8)
Handshake Controls
/DAV0 and RDY0
(P32 and P35)
OEN
Out
In
DS97TAD0300
1.5
2.3V Hysteresis
R = 500 KΩ
Figure 10. Port 0 Configuration
PRELIMINARY
PAD
Auto Latch
1-21