Z89135 Datasheet, PDF (39/66 Pages) Zilog, Inc. – Low-Cost DTAD Controller

Zilog
Z89135/136 (ROMless)
Low-Cost DTAD Controller
SCLK/TCLK divide-by-16 Select (D0). D0 of the SMR control) and/or HALT Mode (where TCLK sources
controls a divide-by-16 prescaler of SCLK/TCLK. The pur- counter/timers and interrupt logic).
1 ^{pose of this control is to selectively reduce device power}
consumption during normal processor execution (SCLK ^{Stop-Mode Recovery Source (D4-D2). These three bits}
of the SMR specify the wake-up source of the Stop-Mode
Recovery (Figure 27 and Table 6).
SMR D4 D3 D2
000
VDD
P31
P32
SMR D4 D3 D2 SMR D4 D3 D2
01 0
10 0
01 1
SMR D4 D3 D2
10 1
P20
P33
P27
P23
Stop-Mode Recovery Edge
Select (SMR)
P33 From Pads
SMR D4 D3 D2
11 0
P20
P27
SMR D4 D3 D2
11 1
To POR
RESET
To P33 Data
Latch and IRQ1
MUX
Digital/Analog Mode
Select (P3M)
Figure 27. Stop-Mode Recovery Source
Table 6. Stop-Mode Recovery Source
SMR:432
D4 D3 D2
Operation
Description of Action
0 0 0 POR and/or external reset recovery
0 0 1 No effect
0 1 0 P31 transition
0 1 1 P32 transition
1 0 0 P33 transition
1 0 1 P27 transition
1 1 0 Logical NOR of P20 through P23
1 1 1 Logical NOR of P20 through P27
Stop-Mode Recovery Delay Select (D5). This bit, if High,
disables the 5 ms /RESET delay after Stop-Mode Recov-
ery. The default configuration of this bit is one. If the “fast”
wake-up is selected, the Stop-Mode Recovery source is
kept active for at least 5 TpC.
Stop-Mode Recovery Edge Select (D6). A 1 in this bit po-
sition indicates that a high level on any one of the recovery
sources wakes the Z89165 from STOP Mode. A 0 indi-
cates low level recovery. The default is 0 on POR .
Cold or Warm Start (D7). This bit is set by the device
upon entering STOP Mode. It is active High, and is 0 (cold)
on POR/WDT /RESET. This bit is Read Only. It is used to
distinguish between cold or warm start.
DS97TAD0300
PRELIMINARY
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