Z89135 Datasheet, PDF (14/66 Pages) Zilog, Inc. – Low-Cost DTAD Controller

Z89135/136 (ROMless)
Low-Cost DTAD Controller
AC CHARACTERISTICS
External I/O or Memory Read and Write Timing Table
No Symbol
Parameter
1
TdA(AS)
Address Valid to /AS Rise Delay
2
TdAS(A)
/AS Rise to Address Float Delay
3
TdAS(DR) /AS Rise to Read Data Req’d Valid
4
TwAS
/AS Low Width
5
TdAZ(DS) Address Float to /DS Fall
6
TwDSR
/DS (Read) Low Width
7
TwDSW
/DS (Write) Low Width
8
TdDSR(DR) /DS Fall to Read Data Req’d Valid
9
ThDR(DS) Read Data to /DS Rise Hold Time
10
TdDS(A)
/DS Rise to Address Active Delay
11
TdDS(AS) /DS Rise to /AS Fall Delay
12
TdR/W(AS) R//W Valid to /AS Rise Delay
13
TdDS(R/W) /DS Rise to R//W Not Valid
14
TdDW(DSW) Write Data Valid to /DS Fall (Write) Delay
15
TdDS(DW) /DS Rise to Write Data Not Valid Delay
16
TdA(DR)
Address Valid to Read Data Req’d Valid
17
TdAS(DS) /AS Rise to /DS Fall Delay
18
TdDI(DS) Data Input Setup to /DS Rise
19
TdDM(AS) /DM Valid to /AS Fall Delay
Notes:
1. When using extended memory timing, add 2 TpC.
2. Timing numbers given are for minimum TpC.
3. See clock cycle dependent characteristics table.
5.0V ±0.25V
Standard Test Load
All timing references use 0.9 V_CC for a logic 1 and 0.1 V_CC for a logic 0.
V_CC
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
Zilog
T_A=0°C to +55°C
Min
Max
25
35
150
35
0
125
75
90
0
40
35
25
35
40
25
180
48
50
20
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
2,3
2,3
1,2,3
2,3
1,2,3
1,2,3
1,2,3
2,3
2,3
2,3
2,3
2,3
2,3
2,3
1,2,3
2,3
1,2,3
2,3
1-14
PRELIMINARY
DS97TAD0300