Z89135 Datasheet, PDF (41/66 Pages) Zilog, Inc. – Low-Cost DTAD Controller

Zilog
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Watch-Dog Timer Mode Register (WDTMR). The WDT is driven by an on-board RC oscillator or external oscillator
is a retriggerable one-shot timer that resets the Z8 if it from the XTAL1 pin. The POR clock source is selected
reaches its terminal count. The WDT is initially enabled by
executing the WDT instruction and refreshed on subse-
with bit 4 of the WDT register (Figure 28). The WDTMR is
accessable only within 64 Z8 clock cyles after POR.
1
quent executions of the WDT instruction. The WDT circuit
WDTMR (FH) 0FH
D7 D6 D5 D4 D3 D2 D1 D0
* Default setting after RESET
WDT TAP
00
01 _*
10
11
INT RC OSC External Clock
5 ms
256 TpC
15 ms
512 TpC
25 ms
1024 TpC
100 ms
4096 TpC
WDT During HALT
0 OFF
1 ON _*
WDT During STOP
0 OFF
1 ON _*
XTAL1/INT RC Select for WDT
0 On-Board RC _*
1 XTAL
W No Effect
R Alway "1"
Figure 28. Watch-Dog Timer Mode Register
DS97TAD0300
PRELIMINARY
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