Z89135 Datasheet, PDF (34/66 Pages) Zilog, Inc. – Low-Cost DTAD Controller

Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Interrupts. The Z8 has six different interrupts from six dif-
ferent sources. The interrupts are maskable and prioritized
(Figure 21). The six sources are divided as follows; three
sources are claimed by Port 3 lines P33-P31, two in
counter/timers, and one by the DSP (Table 4). The Inter-
rupt Mask Register globally or individually enables or dis-
ables the six interrupt requests.When more than one inter-
rupt is pending, priorities are resolved by a programmable
priority encoder that is controlled by the Interrupt Priority
Register. An interrupt machine cycle is activated when an
interrupt request is granted. This disables all subsequent
interrupts, pushes the Program Counter and Status Flags
to the stack, and then branches to the program memory
vector location reserved for that interrupt.
All Z8 interrupts are vectored through locations in the pro-
gram memory. This memory location and the next byte
contain the 16-bit address of the interrupt service routine
for that particular interrupt request. To accommodate
polled interrupt systems, interrupt inputs are masked and
the Interrupt Request Register is polled to determine which
of the interrupt requests need service.
An interrupt resulting from AN1 is mapped into IRQ2, and
an interrupt from AN2 is mapped into IRQ0. Interrupts
IRQ2 and IRQ0 may be rising, falling or both edge trig-
gered, and are programmable by the user. The software
may poll to identify the state of the pin.
Programming bits for the Interrupt Edge Select is located
in the IRQ Register (R250), bits D7 and D6. The configu-
ration is shown in Table 5.
Table 5. IRQ Register
IRQ
D7
D6
0
0
0
1
1
0
1
1
Notes:
F = Falling Edge
R = Rising Edge
Interrupt Edge
P31
P32
F
F
F
R
R
F
R/F
R/F
Clock. The Z89135/136 on-chip oscillator has a high-gain,
parallel-resonant amplifier for connection to a crystal, LC,
ceramic resonator, or any suitable external clock source
(XTAL1 = Input, XTAL2 = Output). The crystal should be
AT cut, 20.48 MHz max., with a series resistance (RS) less
than or equal to 100 Ohms. The system clock (SCLK) is
one half the crystal frequency.
The crystal is connected across XTAL1 and XTAL2 using
capacitors from each pin to ground.
XTAL1
XTAL1
C1
C1
L
XTAL2
XTAL2
C2
C2
XTAL1
XTAL2
Ceramic Resonator or
LC
Crystal
External Clock
Figure 22. Oscillator Configuration
1-34
PRELIMINARY
DS97TAD0300