Z89135 Datasheet, PDF (46/66 Pages) Zilog, Inc. – Low-Cost DTAD Controller

Z89135/136 (ROMless)
Low-Cost DTAD Controller
DSP INTERRUPTS
The DSP processor has three interrupt sources (INT2,
INT1, INT0) (Figure 31). These sources have different pri-
ority levels (Figure 32). The highest priority, the next lower
and the lowest priority level are assigned to INT2, INT1
and INT0, respectively. The DSP does not allow interrupt
nesting (interrupting service routines that are currently be-
Zilog
ing executed). When two interrupt requests occur simulta-
neously the DSP starts servicing the interrupt with the
highest priority level. Figure 33 shows the interprocessor
interrupts mechanism.
Z8_INT
A/D INT
D/A INT
IPR2
IPR1
IPR0
FB DSP
Interrupt Priority Logic
Interrupt Request Logic
FeedBack Z8_INT MPX
INT2
INT1
INT0
Interrupt Mask Logic
INT2
INT1
INT0
CLEAR_INT0
CLEAR_INT1
CLEAR_INT2
ENABLE_INT
Figure 31. DSP Interrupts
INT0
INT1
INT2
DSP Execution
INT2
INT0
INT1
INT2
Figure 32. DSP Interrupt Priority Structure
1-46
Z8 Side
On the Z8, set D1 to
interrupt DSP via DSP INT2.
DSP CON
After serving IRQ3,
set D0 to clear the
interrupt request.
10
9
DSP Side
DSP INT2
After serving INT2,
set D4 to clear the
interrupt request.
4
ICR
(EXT4)
IRQ3 of the Z8
The DSP sets D9 to
interrupt Z8 via Z8 IRQ3.
Figure 33. Interprocessor Interrupts Structure
PRELIMINARY
DS97TAD0300