Z89135 Datasheet, PDF (42/66 Pages) Zilog, Inc. – Low-Cost DTAD Controller

Z89135/136 (ROMless)
Low-Cost DTAD Controller
WDT Time Select (D0,D1). Selects the WDT time period.
It is configured as shown in Table 8.
Table 8. WDT Time Select
Time-out of
D1
D0 Internal RC OSC
0
0
5 ms min
0
1
15 ms min
1
0
25 ms min
1
1
100 ms min
Notes:
TpC = XTAL clock cycle
The default on reset is 15 ms.
Time-out of
XTAL clock
256 TpC
512 TpC
1024 TpC
4096 TpC
Zilog
WDT During Halt (D2). This bit determines whether or not
the WDT is active during HALT Mode. A 1 indicates active
during HALT. The default is 1.
WDT During Stop (D3). This bit determines whether or
not the WDT is active during STOP Mode. Since XTAL
clock is stopped during STOP Mode, the on-board RC has
to be selected as the clock source to the POR counter. A
1 indicates active during STOP. The default is 1.
Clock Source for WDT (D4). This bit determines which
oscillator source is used to clock the internal POR and
WDT counter chain. If the bit is a 1, the internal RC oscil-
lator is bypassed and the POR and WDT clock source is
driven from the external pin, XTAL1. The default configu-
ration of this bit is 0 which selects the RC oscillator
.
/RESET
4 Clock
Filter
Clear
CLK
18 Clock RESET
Generator
RESET
WDT Select
(WDTMR)
CK Source
Select
(WDTMR)
XTAL
WDT TAP SELECT
RC
OSC.
5 ms POR 5 ms 15 ms 25 ms 100 ms
M
U
X
CK
WDT/POR Counter Chain
CLR
VDD
2V REF.
2V Operating
+ Voltage Det.
-
From Stop
Mode
Recovery
Source
12 ns Glitch Filter
WDT
Stop Delay
Select (SMR)
Figure 29. Resets and WDT
Internal
RESET
1-42
PRELIMINARY
DS97TAD0300