Z89135 Datasheet, PDF (40/66 Pages) Zilog, Inc. – Low-Cost DTAD Controller

Z89135/136 (ROMless)
Low-Cost DTAD Controller
FUNCTIONAL DESCRIPTION (Continued)
DSP Control Register (DSPCON). The DSPCON register
controls various aspects of the Z8 and the DSP. It can con-
figure the internal system clock (SCLK) or the Z8, RESET,
Zilog
and HALT of the DSP, and control the interrupt interface
between the Z8 and the DSP (Table 7).
Table 7. DSP Control Register
(F) 0CH [Read/Write]
Field
DSPCON (F)0CH
Z8_SCLK
DSP_Reset
DSP_Run
Reserved
IntFeedback
IntFeedback
Position
76------
--5-----
---4----
----32--
------1-
-------0
Attrib
R/W
R
W
R/W
W
R
R
W
R
W
Value
00
01
1x
0
1
0
1
1
0
1
0
Label
2.5 MHz (OSC/8)
5 MHz (OSC/4)
10 MHz (OSC/2)
Return “0
No effect
Reset DSP
HALT_DSP
Run_DSP
No effect
Return “0”
No effect
FB_DSP_INT2
Set DSP_INT2
No effect
FB_Z8_IRQ3
Clear IRQ3
No effect
Z8 IRQ3 (D0). This bit, when read, indicates the status of
Z8 IRQ3. Z8 IRQ3 is set by the DSP by writing to D9 of
DSP External Register 4 (ICR). By writing a 1 to this bit, Z8
IRQ3 is Reset.
DSP INT2 (D1). This bit is linked to DSP INT2. Writing a 1
to this bit sets DSP INT2. Reading this bit indicates the sta-
tus of DSP INT2.
DSP RESET (D5). Setting this bit to 1 will reset the DSP.
If the DSP was in HALT Mode, this bit is automatically pre-
set to 1. Writing a 0 has no effect.
Z8 SCLK (D8-D7). These bits define the SCLK frequency
of the Z8. The oscillator can be divided by 8, 4, or 2. After
a reset, both of these bits are defaulted to 00.
DSP RUN (D4). This bit defines the HALT Mode of the
DSP. If this bit is set to 0, then the DSP clock is turned off
to minimize power consumption. After this bit is set to 1,
then the DSP will continue code execution from where it
was halted. After a hardware reset, this bit is reset to 1.
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PRELIMINARY
DS97TAD0300