Z89135 Datasheet, PDF (47/66 Pages) Zilog, Inc. – Low-Cost DTAD Controller

Zilog
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Table 13. EXT4 DSP Interrupt Control Register (ICR) Definition
Field
Position
Attrib
Value
Label
1
DSP_IRQ2
f---------------
R
1
Set_IRQ2
0
Reset_IRQ2
f---------------
W
No effect
DSP_IRQ1
-e--------------
R
1
Set_IRQ1
0
Reset_IRQ1
-e--------------
W
No effect
DSP_IRQ0
--d-------------
R
1
Set_IRQ0
0
Reset_IRQ0
--d-------------
W
No effect
DSP_MaskINT2
---c------------
R/W
1
Enable_INT2
0
Disable_INT2
DSP_MaskINT1
----b-----------
R/W
1
Enable_INT1
0
Disable_INT1
DSP_MaskINT0
-----a----------
R/W
1
Enable_INT0
0
Disable_INT0
Z8_IRQ3
------9---------
R
Return "0"
------9---------
W
1
Set_Z8_IRQ3
0
Reset_Z8_IRQ3
DSPintEnable
-------8--------
R/W
1
Enable
0
Disable
DSP_IPR2
--------7-------
R/W
Binary
IPR2
DSP_IPR1
---------6------
R/W
Binary
IPR1
DSP_IPR0
----------5-----
R/W
Binary
IPR0
Clear_IRQ2
-----------4----
R
Return "0"
-----------4----
W
1
Clear_IRQ2
0
Has_no_effect
Clear_IRQ1
------------3---
R
Return "0"
------------3---
W
1
Clear_IRQ1
0
No effect
Clear_IRQ0
-------------2--
R
Return "0"
-------------2--
W
1
Clear_IRQ0
0
No effect
Reserved
--------------10
W
No effect "0"
R
Interrupt Control Register (ICR). The ICR is mapped into
EXT4 of the DSP (Table 13). The bits are defined as fol-
lows:
output register (conversion done). This bit asserts IRQ1 of
the DSP and can be cleared by writing to the
Clear_IRQ1bit.
DSP_IRQ2 (Z8 Interrupt). This bit can be read by both Z8
and DSP and can be set only by writing to the Z8 expand-
ed Register File (Bank F, ROC, bit 0). This bit asserts IRQ2
of the DSP and can be cleared by writing to the
Clear_IRQ2 bit.
DSP_IRQ1 (A/D Interrupt). This bit can be read by the
DSP only and is set when valid data is present at the A/D
DSP_IRQ0 (D/A Interrupt). This bit can be read by DSP
only and is set by Timer3. This bit assists IRQ0 of the DSP
and can be cleared by writing to the Clear_IRQ0 bit.
DSP_MaskIntX. These bits can be accessed by the DSP
only. Writing a 1 to these locations allows the INT to be
serviced, while writing a 0 masks the corresponding INT
off.
DS97TAD0300
PRELIMINARY
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