Z89135 Datasheet, PDF (35/66 Pages) Zilog, Inc. – Low-Cost DTAD Controller

Zilog
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Counter/Timers. There are two 8-bit programmable pass mode) or to automatically reload the initial value and
counter/timers (T0-T1), each driven by its own 6-bit pro- continue counting (modulo-n continuous mode).
grammable prescaler. The T1 prescaler is driven by inter-
nal or external clock sources; however, the T0 prescaler is
The counters, but not the prescalers, are read at any time
1
driven by the internal clock only (Figure 23).
without disturbing their value or count mode. The clock
source for T1 is user-definable and is either the internal mi-
The 6-bit prescalers can divide the input frequency of the croprocessor clock divided by four, or an external signal in-
clock source by any integer number from 1 to 64. Each put through Port 31. The Timer Mode register configures
prescaler drives its counter, which decrements the value the external timer input (P31) as an external clock, a trig-
(1 to 256) that has been loaded into the counter. When the ger input that can be retriggerable or non-retriggerable, or
counter reaches the end of the count, a timer interrupt re- as a gate input for the internal clock. The counter/timers
quest, IRQ4 (T0) or IRQ5 (T1), is generated.
can be cascaded by connecting the T0 output to the input
of T1.
The counters can be programmed to start, stop, restart to
continue, or restart from the initial value. The counters can
also be programmed to stop upon reaching zero (single
DSP Clock
÷2
D7, D6
(F) OC
(DSP CON)
÷2
D0,D1
(SMR)
÷ 16
÷2
OSC
T0, T2, T3
Internal Data Bus
Write
Write
Read
PRE0
Initial Value
Register
T0
Initial Value
Register
T0
Current Value
Register
÷4
Internal
Clock
6-Bit
Down
Counter
8-bit
Down
Counter
IRQ4
External Clock
÷2
TOUT
P36
Clock
Logic
÷4
Internal Clock
Gated Clock
Triggered Clock
TIN P31
6-Bit
Down
Counter
8-Bit
Down
Counter
IRQ5
PRE1
Initial Value
Register
T1
Initial Value
Register
T1
Current Value
Register
Write
Write
Read
Internal Data Bus
Figure 23. Counter/Timer Block Diagram
DS97TAD0300
PRELIMINARY
1-35