Z89135 Datasheet, PDF (55/66 Pages) Zilog, Inc. – Low-Cost DTAD Controller

Zilog
Expanded Register Bank F
PCON (FH) 00H
D7 D6 D5 D4 D3 D2 D1 D0
Note: Reset condition is 11111110
R Always "1"
W 0 P34,P37
Standard output
1 P34,P37
Comparator output
R Always "1"
W No effect
Figure 56. Port Configuration Register (PCON)
(F) 00H [Write Only]
P4D (FH) 02H
D7 D6 D5 D4 D3 D2 D1 D0
Data
Figure 57. Port 4 Data Register
(F) 02H [Write Only]
Z89135/136 (ROMless)
Low-Cost DTAD Controller
P5M (FH) 05H
1
D7 D6 D5 D4 D3 D2 D1 D0
* Default setting after Reset
P50-P57 I/O Definition
0 Defines Bit as Output
1 Defines Bit as Input*
Returns "FF" Upon Read
Figure 60. Port 5 Mode Register (PCON)
(F) 05H [Write Only]
P45CON (FH) 06H
D7 D6 D5 D4 D3 D2 D1 D0
* Default setting after Reset
Port 4 Configuration Bit
0 Open Drain *
1 Push-pull Active
Reserved
Port 5 Configuration Bit
0 Open Drain *
1 Push-pull Active
Reserved
Figure 61. Port 4 and 5 Configuration Register
(F) 06H [Write Only]
P4M (FH) 03H
D7 D6 D5 D4 D3 D2 D1 D0
P40-P47 I/O Definition
0 Defines Bit as Output
1 Defines Bit as Input
Returns "FF" Upon Read
Figure 58. Port 4 Mode Register
(F) 03H [Write Only]
P5D (FH) 04H
D7 D6 D5 D4 D3 D2 D1 D0
Data
Figure 59. Port 5 Data Register (PCON)
(F) 04H [Read/Write]
SMR (FH) 0BH
D7 D6 D5 D4 D3 D2 D1 D0
*
Default SettingAfter Reset
† Reset After Stop-Mode Recovery
W 00 SCLK/TCLK Not Divide by 16†
01 SCLK/TCLK Not Divide by 16
10 SCLK/TCLK Divide by 16
11 SCLK/TCLK Divide by 16
R Always "1"
W 000 POR only*
001 No effect
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
R Always "1"
W 0 Stop delay on*
1 Stop delay off
R Always "1"
W 0 Low Stop Recovery Level*
1 High Stop Recovery Level
R Always "1"
W No effect
R 0 POR*
1 Stop-Mode Recovery
Figure 62. Stop-Mode Recovery Register
(F) 07H [Read/Write]
DS97TAD0300
PRELIMINARY
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