Z89135 Datasheet, PDF (56/66 Pages) Zilog, Inc. – Low-Cost DTAD Controller

Z89135/136 (ROMless)
Low-Cost DTAD Controller
Field
DSPCON (F)0CH
Z8_SCLK
DSP_Reset
DSP_Run
Reserved
IntFeedback
Table 18. DSP Control Register
(F) 0FH [Read/Write]
Position
76------
--5-----
---4----
----32--
------1-
-------0
Attrib
R/W
R
W
R/W
R
W
R
W
Value
00
0.1
1x
0
1
0
1
xx
1
0
1
0
Label
2.5 MHz (OSC/8)
5 MHz (OSC/4)
10 MHz (OSC/2)
Return “0”
No effect
Reset DSP
Halt_DSP
Run_DSP
Return “0”
No effect
FB_DSP_INT2
Set DSP_INT2
No effect
FB_Z8_IRQ3
Clear IRQ 3
No effect
WDTMR (FH) 0FH
D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP
00
01 _*
10
11
INT RC OSC
5 ms
15 ms
25 ms
100 ms
External Clock
256 TpC
512 TpC
1024 TpC
4096 TpC
WDT During HALT
0 OFF
1 ON _*
WDT During STOP
0 OFF
1 ON _*
XTAL1/INT RC Select for WDT
0 On-Board RC _*
1 XTAL
Reserved
* Default setting after RESET
Note: The WDTMR Register is only accessed within 64 Z8^®
clock cycles after POR.
Figure 63. Watch-Dog Timer Mode Register
(F) 0FH [Read/Write]
Zilog
1-56
PRELIMINARY
DS97TAD0300