DS541 Datasheet, PDF (9/27 Pages) Xilinx, Inc – Defense Grade Platform Flash In-System Programmable Configuration PROM

—PRODUCT OBSOLETE / UNDER OBSOLESCENCE—
Defense Grade Platform Flash In-System Programmable Configuration PROM
X-Ref Target - Figure 4
PROM 0
REV 0
(8 Mbits)
REV 1
(8 Mbits)
REV 2
(8 Mbits)
REV 3
(8 Mbits)
PROM 0
REV 0
(8 Mbits)
REV 1
(8 Mbits)
REV 2
(16 Mbits)
PROM 0
REV 0
(16 Mbits)
REV 1
(16 Mbits)
PROM 0
REV 0
(8 Mbits)
REV 1
(24 Mbits)
PROM 0
REV 0
(32 Mbits)
4 Design Revisions 3 Design Revisions
2 Design Revisions
(a) Design Revision storage examples for a single XQF32P PROM
PROM 0
REV 0
(16 Mbits)
REV 1
(16 Mbits)
PROM 0
REV 0
(16 Mbits)
REV 1
(16 Mbits)
PROM 0
REV 0
(32 Mbits)
PROM 0
REV 0
(16 Mbits)
REV 1
(16 Mbits)
1 Design Revision
PROM 0
REV 0
(32 Mbits)
PROM 1
REV 2
(16 Mbits)
REV 3
(16 Mbits)
PROM 1
REV 2
(32 Mbits)
PROM 1
REV 1
(32 Mbits)
PROM 1
REV 1
(32 Mbits)
PROM 1
REV 0
(32 Mbits)
4 Design Revisions 3 Design Revisions
2 Design Revisions
(b) Design Revision storage examples spanning two XQF32P PROMs
1 Design Revision
ds541_04_070906
Figure 4: Design Revision Storage Examples
Initiating FPGA Configuration
The options for initiating FPGA configuration via the Platform Flash PROM include:
• Automatic configuration on power up
• Applying an external PROG_B (or PROGRAM) pulse
• Applying the JTAG CONFIG instruction
Following the FPGA’s power-on sequence or the assertion of the PROG_B (or PROGRAM) pin the FPGA’s configuration
memory is cleared, the configuration mode is selected, and the FPGA is ready to accept a new configuration bitstream. The
FPGA’s PROG_B pin can be controlled by an external source, or alternatively, the Platform Flash PROMs incorporate a CF
pin that can be tied to the FPGA’s PROG_B pin. Executing the CONFIG instruction through JTAG pulses the CF output Low
once for 300-500 ns, resetting the FPGA and initiating configuration. The iMPACT software can issue the JTAG CONFIG
command to initiate FPGA configuration by setting the Load FPGA option.
When using the XQF32P Platform Flash PROM with design revisioning enabled, the CF pin should always be connected to
the PROG_B (or PROGRAM) pin on the FPGA to ensure that the current design revision selection is sampled when the
FPGA is reset. The XQF32P PROM samples the current design revision selection from the external REV_SEL pins or the
internal programmable Revision Select bits on the rising edge of CF. When the JTAG CONFIG command is executed, the
XQF32P samples the new design revision selection before initiating the FPGA configuration sequence. When using the
XQF32P Platform Flash PROM without design revisioning, if the CF pin is not connected to the FPGA PROG_B (or
PROGRAM) pin, then the XQF32P CF pin must be tied High.
DS541 (v3.0) August 5, 2015
Product Specification
www.xilinx.com
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