DS541 Datasheet, PDF (11/27 Pages) Xilinx, Inc – Defense Grade Platform Flash In-System Programmable Configuration PROM

—PRODUCT OBSOLETE / UNDER OBSOLESCENCE—
Defense Grade Platform Flash In-System Programmable Configuration PROM
Table 6 shows the truth table of the XQF32P PROM inputs and outputs.
Table 6: Truth Table for XQF32P PROM Control Inputs
OE/RESET
High
Control Inputs
CE
CF
Low
High
BUSY⁽⁵⁾
Low
Internal Address
If address < TC⁽²⁾ and
address < EA⁽³⁾ : increment
If address < TC⁽²⁾ and
address = EA⁽³⁾ : don't change
DATA
Active
High-Z
Else
If address = TC⁽²⁾ : don't change
High-Z
High
High
Low
X ⁽¹⁾
Low
Low
Low
High
High
↑
X ⁽¹⁾
X ⁽¹⁾
High Unchanged
X⁽¹⁾ Reset⁽⁴⁾
X⁽¹⁾ Held reset⁽⁴⁾
X⁽¹⁾ Held reset⁽⁴⁾
Active and
Unchanged
Active
High-Z
High-Z
Outputs
CEO CLKOUT
High
Active
ICC
Active
High
High-Z Reduced
Low
High-Z Reduced
High
Active
Active
High
High
High
Active
High-Z
High-Z
Active
Active
Standby
Notes:
1. X = don’t care.
2. TC = Terminal Count = highest address value.
3. For the XQF32P with Design Revisioning enabled, EA = end address (last address in the selected design revision).
4. For the XQF32P with Design Revisioning enabled, Reset = address reset to the beginning address of the selected bank. If Design
Revisioning is not enabled, then Reset = address reset to address 0.
5. The BUSY input is only enabled when the XQF32P is programmed for parallel data output and decompression is not enabled.
DS541 (v3.0) August 5, 2015
Product Specification
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