DS541 Datasheet, PDF (16/27 Pages) Xilinx, Inc – Defense Grade Platform Flash In-System Programmable Configuration PROM

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Defense Grade Platform Flash In-System Programmable Configuration PROM
Table 12: XQF32P PROM as Configuration Slave with CLK Input Pin as Clock Source (Cont’d)
Symbol
Description
T_CYC
T_LC
T_HC
T_SCE
T_HCE
T_HOE
T_SB
T_HB
T_SXT
T_HXT
T_SRV
T_HRV
Clock period⁽⁶⁾ (serial mode) when V_CCO = 3.3V or 2.5V
Clock period⁽⁶⁾ (serial mode) when V_CCO = 1.8V
Clock period⁽⁶⁾ (parallel mode) when V_CCO = 3.3V or 2.5V
Clock period⁽⁶⁾ (parallel mode) when V_CCO = 1.8V
CLK Low time⁽³⁾ when V_CCO = 3.3V or 2.5V
CLK Low time⁽³⁾ when V_CCO = 1.8V
CLK High time⁽³⁾ when V_CCO = 3.3V or 2.5V
CLK High time⁽³⁾ when V_CCO = 1.8V
CE setup time to CLK (guarantees proper counting)⁽³⁾ when V_CCO = 3.3V or 2.5V
CE setup time to CLK (guarantees proper counting)⁽³⁾ when V_CCO = 1.8V
CE hold time (guarantees counters are reset)⁽⁴⁾ when V_CCO = 3.3V or 2.5V
CE hold time (guarantees counters are reset)⁽⁴⁾ when V_CCO = 1.8V
OE/RESET hold time (guarantees counters are reset)⁽⁵⁾ when V_CCO = 3.3V or 2.5V
OE/RESET hold time (guarantees counters are reset)⁽⁵⁾ when V_CCO = 1.8V
BUSY setup time to CLK when V_CCO = 3.3V or 2.5V⁽⁸⁾
BUSY setup time to CLK when V_CCO = 1.8V⁽⁸⁾
BUSY hold time to CLK when V_CCO = 3.3V or 2.5V⁽⁸⁾
BUSY hold time to CLK when V_CCO = 1.8V⁽⁸⁾
EN_EXT_SEL setup time to CF, CE or OE/RESET when V_CCO = 3.3V or 2.5V⁽⁸⁾
EN_EXT_SEL setup time to CF, CE or OE/RESET when V_CCO = 1.8V⁽⁸⁾
EN_EXT_SEL hold time from CF, CE or OE/RESET when V_CCO = 3.3V or 2.5V⁽⁸⁾
EN_EXT_SEL hold time from CF, CE or OE/RESET when V_CCO = 1.8V⁽⁸⁾
REV_SEL setup time to CF, CE or OE/RESET when V_CCO = 3.3V or 2.5V⁽⁸⁾
REV_SEL setup time to CF, CE or OE/RESET when V_CCO = 1.8V⁽⁸⁾
REV_SEL hold time from CF, CE or OE/RESET when V_CCO = 3.3V or 2.5V⁽⁸⁾
REV_SEL hold time from CF, CE or OE/RESET when V_CCO = 1.8V⁽⁸⁾
XQF32P
Min
Max
30
–
30
–
35
–
35
–
12
–
12
–
12
–
12
–
30
–
30
–
2000
–
2000
–
2000
–
2000
–
12
–
12
–
8
–
8
–
300
–
300
–
300
–
300
–
300
–
300
–
300
–
300
–
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. AC test load = 30 pF for XQF32P.
2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady-state active levels.
3. All AC parameters are measured with V_IL = 0.0V and V_IH = 3.0V.
4. If T_HCE High < 2 µs, T_CE = 2 µs.
5. If T_HOE Low < 2 µs, T_OE = 2 µs.
6. This is the minimum possible T_CYC. Actual T_CYC = T_CAC + FPGA Data setup time. Example: With the XCF32P in serial mode with V_CCO at
3.3V, if FPGA data setup time = 15 ns, then the actual T_CYC = 25 ns +15 ns = 40 ns.
7. Guaranteed by design; not tested.
8. CF, EN_EXT_SEL, REV_SEL[1:0], and BUSY are inputs.
9. When JTAG CONFIG command is issued, PROM drives CF Low for at least the T_HCF minimum.
DS541 (v3.0) August 5, 2015
Product Specification
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