DS541 Datasheet, PDF (17/27 Pages) Xilinx, Inc – Defense Grade Platform Flash In-System Programmable Configuration PROM

—PRODUCT OBSOLETE / UNDER OBSOLESCENCE—
Defense Grade Platform Flash In-System Programmable Configuration PROM
XQF32P PROM as Configuration Master with CLK Input Pin as Clock Source
X-Ref Target - Figure 7
CE
OE/RESET
CLK
CLKOUT
BUSY
(optional)
DATA
CF
TCECC
TOECC
TOE
TCE
THCF
TCF
TCFCC
TCYCO
TLC
THC
TCLKO
TSB
THB _TCCDD
TCOH
TDDC
THCE
THOE
TEOH
TDF
EN_EXT_SEL
REV_SEL[1:0]
TSXT
TSRV
THXT
THRV
TSXT
TSRV
THXT
THRV
Note: 8 CLKOUT cycles are output after CE rising edge, before CLKOUT
is 3-stated, if OE/RESET remains High, and terminal count has not been reached.
Figure 7: XQF32P PROM as Configuration Master with CLK Input Pin as Clock Source
DS541_07_020811
Table 13: XQF32P PROM as Configuration Master with CLK Input Pin as Clock Source
Symbol
Description
XQF32P
Min
Max
T_HCF
T_CF
T_OE
T_CE
T_EOH
T_DF
T_CYCO
CF hold time to guarantee design revision selection is sampled
when V_CCO = 3.3V or 2.5V⁽¹¹⁾
CF hold time to guarantee design revision selection is sampled
when V_CCO = 1.8V⁽¹¹⁾
CF to data delay when V_CCO = 3.3V or 2.5V
CF to data delay when V_CCO = 1.8V
OE/RESET to data delay⁽⁶⁾ when V_CCO = 3.3V or 2.5V
OE/RESET to data delay⁽⁶⁾ when V_CCO = 1.8V
CE to data delay⁽⁵⁾ when V_CCO = 3.3V or 2.5V
CE to data delay⁽⁵⁾ when V_CCO = 1.8V
Data hold from CE, OE/RESET, or CF when V_CCO = 3.3V or 2.5V
Data hold from CE, OE/RESET, or CF when V_CCO = 1.8V
CE or OE/RESET to data float delay⁽²⁾ when V_CCO = 3.3V or 2.5V
CE or OE/RESET to data float delay⁽²⁾ when V_CCO = 1.8V
Clock period⁽⁷⁾ (serial mode) when V_CCO = 3.3V or 2.5V
Clock period⁽⁷⁾ (serial mode) when V_CCO = 1.8V
Clock period⁽⁷⁾ (parallel mode) when V_CCO = 3.3V or 2.5V
Clock period⁽⁷⁾ (parallel mode) when V_CCO = 1.8V
300
–
300
–
–
25
–
25
–
30
–
30
–
30
–
30
5
–
5
–
–
45
–
45
30
–
30
–
35
–
35
–
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS541 (v3.0) August 5, 2015
Product Specification
www.xilinx.com
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