DS541 Datasheet, PDF (23/27 Pages) Xilinx, Inc – Defense Grade Platform Flash In-System Programmable Configuration PROM

—PRODUCT OBSOLETE / UNDER OBSOLESCENCE—
Defense Grade Platform Flash In-System Programmable Configuration PROM
Pinouts and Pin Descriptions
XQF32P VOG48 Pin Names and Descriptions
The XQF32P Platform Flash PROM is available in the VOG48 package. Table 16 provides a list of the pin names and
descriptions for the XQF32P 48-pin VOG48 plastic, thin, small outline package (TSOP).
Table 16: XQF32P Pin Names and Descriptions (VOG48)
Pin Name
Boundary
Scan Order
Boundary
Scan
Function
Pin Description
D0
28
Data Out D0 is the DATA output pin to provide data for configuring an FPGA in
27
Output Enable
serial mode.
D0-D7 are the DATA output pins to provide parallel data for configuring a
D1
26
Data Out Xilinx FPGA in SelectMap (parallel) mode.
25
Output Enable
The D0 output is set to a high-impedance state during ISPEN (when not
clamped).
D2
24
Data Out _{The D1-D7 outputs are set to a high-impedance state during ISPEN}
23
Output Enable
(when not clamped) and when serial mode is selected for configuration.
The D1-D7 pins can be left unconnected when the PROM is used in serial
D3
22
Data Out mode.
21
Output Enable
D4
20
Data Out
19
Output Enable
D5
18
Data Out
17
Output Enable
D6
16
Data Out
15
Output Enable
D7
14
Data Out
13
Output Enable
CLK
01
Data In Configuration Clock Input. An internal programmable control bit selects
between the internal oscillator and the CLK input pin as the clock source
to control the configuration sequence. Each rising edge on the CLK input
increments the internal address counter if the CLK input is selected, CE
is Low, OE/RESET is High, BUSY is Low (parallel mode only), and CF is
High.
OE/RESET
04
Data In Output Enable/Reset (Open-Drain I/O).
03
Data Out ^{When Low, this input holds the address counter reset and the DATA and}
CLKOUT outputs are placed in a high-impedance state. This is a
02
Output Enable bidirectional open-drain pin that is held Low while the PROM completes
the internal power-on reset sequence. Polarity is not programmable.
CE
00
Data In Chip Enable Input. When CE is High, the device is put into low-power
standby mode, the address counter is reset, and the DATA and CLKOUT
outputs are placed in a high-impedance state.
CF
11
Data In Configuration Pulse (Open-Drain I/O). As an output, this pin allows the
JTAG CONFIG instruction to initiate FPGA configuration without
powering down the FPGA. This is an open-drain signal that is pulsed Low
10
Data Out _{by the JTAG CONFIG command. As an input, on the rising edge of CF,}
the current design revision selection is sampled and the internal address
counter is reset to the start address for the selected revision. If unused,
09
Output Enable _{the CF pin must be pulled High using an external 4.7 KΩ pull-up to VCCO.}
48-pin
TSOP
VOG48
28
29
32
33
43
44
47
48
12
11
13
6
DS541 (v3.0) August 5, 2015
Product Specification
www.xilinx.com
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