DS541 Datasheet, PDF (19/27 Pages) Xilinx, Inc – Defense Grade Platform Flash In-System Programmable Configuration PROM

—PRODUCT OBSOLETE / UNDER OBSOLESCENCE—
Defense Grade Platform Flash In-System Programmable Configuration PROM
Table 13: XQF32P PROM as Configuration Master with CLK Input Pin as Clock Source (Cont’d)
Symbol
Description
XQF32P
Min
Max
Units
T_HRV
REV_SEL hold time from CF, CE, or OE/RESET when V_CCO = 3.3V or 2.5V
REV_SEL hold time from CF, CE, or OE/RESET when V_CCO = 1.8V
300
–
ns
300
–
ns
Notes:
1. AC test load = 30 pF for XQF32P.
2. Float delays are measured with 5 pF AC loads.Transition is measured at ±200 mV from steady-state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with V_IL = 0.0V and V_IH = 3.0V.
5. If T_HCE High < 2 µs, T_CE = 2 µs.
6. If T_HOE Low < 2 µs, T_OE = 2 µs.
7. This is the minimum possible T_CYCO. Actual T_CYCO = T_CCDD + FPGA Data setup time. Example: With the XQF32P in serial mode with V_CCO
at 3.3V, if FPGA Data setup time = 15 ns, then the actual T_CYCO = 25 ns +15 ns = 40 ns.
8. The delay before the enabled CLKOUT signal begins clocking data out of the device is dependent on the clocking configuration. The delay
before CLKOUT is enabled increases if decompression is enabled.
9. Slower CLK frequency option can be required to meet the FPGA data sheet setup time.
10. When decompression is enabled, the CLKOUT signal becomes a controlled clock output. When decompressed data is available, CLKOUT
toggles at ½ the source clock frequency (either ½ the selected internal clock frequency or ½ the external CLK input frequency). When
decompressed data is not available, the CLKOUT pin is parked High. If CLKOUT is used, then it must be pulled High externally using a 4.7kΩ
pull-up to V_CCO.
11. When JTAG CONFIG command is issued, PROM drives CF Low for at least the T_HCF minimum.
XQF32P PROM as Configuration Master with Internal Oscillator as Clock Source
X-Ref Target - Figure 8
CE
OE/RESET
THCE
THOE
CLKOUT
BUSY
(optional)
DATA
CF
TCEC
TOEC
TOE
TCE
THCF
TCF
TCFC
TSB
THB _TCDD
TDDC
TCOH
TEOH
TDF
EN_EXT_SEL
REV_SEL[1:0]
TSXT
TSRV
THXT
THRV
TSXT
TSRV
THXT
THRV
Note: 8 CLKOUT cycles are output after CE rising edge, before CLKOUT
is 3-stated, if OE/RESET remains High, and terminal count has not been reached.
DS541_08_020811
Figure 8: XQF32P PROM as Configuration Master with Internal Oscillator as Clock Source
DS541 (v3.0) August 5, 2015
Product Specification
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