DS541 Datasheet, PDF (4/27 Pages) Xilinx, Inc – Defense Grade Platform Flash In-System Programmable Configuration PROM

—PRODUCT OBSOLETE / UNDER OBSOLESCENCE—
Defense Grade Platform Flash In-System Programmable Configuration PROM
Read Protection
The read protect security bit can be set by the user to prevent the internal programming pattern from being read or copied
via JTAG. Read protection does not prevent write operations. For the XQF32P PROM the read protect security bit can be set
for individual design revisions, and resetting the read protect bit requires erasing the particular design revision.
Write Protection
The XQF32P PROM device also allows the user to write protect (or lock) a particular design revision to prevent inadvertent
erase or program operations. Once set, the write protect security bit for an individual design revision must be reset (using the
UNLOCK command followed by ISC_ERASE command) before an erase or program operation can be performed.
Table 2: XQF32P Design Revision Data Security Options
Read Protect
Write Protect
Reset (default)
Reset (default)
Set
Set
Reset (default)
Set
Reset (default)
Set
Read/Verify
Inhibited
–
–
✓
✓
Program Inhibited Erase Inhibited
–
–
✓
✓
–
–
✓
✓
IEEE 1149.1 Boundary-Scan (JTAG)
The Platform Flash PROM family is compatible with the IEEE 1149.1 boundary-scan standard and the IEEE 1532 in-system
configuration standard. A Test Access Port (TAP) and registers are provided to support all required boundary scan
instructions, as well as many of the optional instructions specified by IEEE Std. 1149.1. In addition, the JTAG interface is
used to implement in-system programming (ISP) to facilitate configuration, erasure, and verification operations on the
Platform Flash PROM device. Table 3 lists the required and optional boundary-scan instructions supported in the Platform
Flash PROMs. Refer to the IEEE Std. 1149.1 specification for a complete description of boundary-scan architecture and the
required and optional instructions.
Note: The XQF32P JTAG TAP pause states are not fully compliant with the JTAG 1149.1 specification. If a temporary pause of a JTAG
shift operation is required, then stop the JTAG TCK clock and maintain the JTAG TAP within the JTAG Shift-IR or Shift-DR TAP state. Do
not transition the XQF32P JTAG TAP through the JTAG Pause-IR or Pause-DR TAP state to temporarily pause a JTAG shift operation.
Table 3: Platform Flash PROM Boundary Scan Instructions
Boundary-Scan Command
XQF32P IR[15:0]
(Hex)
Instruction Description
Required Instructions
BYPASS
FFFF
Enables BYPASS.
SAMPLE/PRELOAD
0001
Enables boundary-scan SAMPLE/PRELOAD operation.
EXTEST
0000
Enables boundary-scan EXTEST operation.
Optional Instructions
CLAMP
00FA
Enables boundary-scan CLAMP operation.
HIGHZ
00FC
Places all outputs in high-impedance state simultaneously.
IDCODE
00FE
Enables shifting out 32-bit IDCODE.
USERCODE
00FD
Enables shifting out 32-bit USERCODE.
Platform Flash PROM Specific Instructions
CONFIG
00EE
Initiates FPGA configuration by pulsing CF pin Low once (for the XQF32P, this
command also resets the selected design revision based on either the external
REV_SEL[1:0] pins or on the internal design revision selection bits).⁽¹⁾
Notes:
1. For more information see Initiating FPGA Configuration, page 9.
DS541 (v3.0) August 5, 2015
Product Specification
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