DS541 Datasheet, PDF (1/27 Pages) Xilinx, Inc – Defense Grade Platform Flash In-System Programmable Configuration PROM

—PRODUCT OBSOLETE / UNDER OBSOLESCENCE—
Defense Grade Platform Flash In-System
Programmable Configuration PROM
DS541 (v3.0) August 5, 2015
Features
• In-System Programmable PROM for Configuration of
Xilinx FPGAs
• Low-Power Advanced CMOS NOR FLASH Process
• Endurance of 20,000 Program/Erase Cycles
• Operation over Full Military Temperature Range
(–55°C to +125°C)
• IEEE Standard 1149.1/1532 Boundary-Scan (JTAG)
Support for Programming, Prototyping, and Testing
• JTAG Command Initiation of Standard FPGA
Configuration
• Cascadable for Storing Longer or Multiple Bitstreams
• Dedicated Boundary-Scan (JTAG) I/O Power Supply
(V_CCJ)
Product Specification
• I/O Pins Compatible with Voltage Levels Ranging From
1.8V to 3.3V
• Design Support Using the Xilinx Alliance ISE™ and
Foundation ISE Series Software Packages
• XQF32P
• 1.8V Supply Voltage
• Serial or Parallel FPGA Configuration Interface
(up to 33 MHz)
• Available in Small-Footprint VOG48 Package
• Design Revision Technology Enables Storing and
Accessing Multiple Design Revisions for
Configuration
• Built-In Data Decompressor Compatible with Xilinx
Advanced Compression Technology
Table 1: Xilinx Defense Grade Platform Flash PROM Features
Device Density V_CCINT V_CCO Range V_CCJ Range
XQF32P 32 Mbit 1.8V 1.8V – 3.3V 2.5V – 3.3V
Packages
VOG48
Program
In-system
via JTAG
✓
Serial
Config.
Parallel
Config.
Design
Revisioning
Compression
✓
✓
✓
✓
Description
This data sheet describes the defense-grade version of the Platform Flash series of in-system programmable configuration
PROMs. Available in 32 Megabit (Mbit) density, this PROM provides an easy-to-use, cost-effective, and reprogrammable
method for storing large Xilinx FPGA configuration bitstreams. The 32-Mbit PROM supports Master Serial, Slave Serial,
Master SelectMAP, and Slave SelectMAP FPGA configuration modes (Figure 1).
X-Ref Target - Figure 1
CLK
CE
EN_EXT_SEL
OE/RESET BUSY
OSC
TCK
TMS
TDI
TDO
Control
and
JTAG
Interface
Data
Address
Memory
Data
Decompressor
Serial
or
Parallel
Interface
CF
REV_SEL [1:0]
Figure 1: XQF32P Platform Flash PROM Block Diagram
CLKOUT
CEO
DATA (D0)
(Serial/Parallel Mode)
D[1:7]
(Parallel Mode)
DS541_01_111706
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DS541 (v3.0) August 5, 2015
Product Specification
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