DS541 Datasheet, PDF (2/27 Pages) Xilinx, Inc – Defense Grade Platform Flash In-System Programmable Configuration PROM

—PRODUCT OBSOLETE / UNDER OBSOLESCENCE—
Defense Grade Platform Flash In-System Programmable Configuration PROM
When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. With CF High, a short
access time after CE and OE are enabled, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN
pin. New data is available a short access time after each rising clock edge. The FPGA generates the appropriate number of
clock pulses to complete the configuration.
When the FPGA is in Slave Serial mode, the PROM and the FPGA are both clocked by an external clock source, or
optionally, the PROM can be used to drive the FPGA’s configuration clock.
The XQF32P defense-grade version of the Platform Flash PROM also supports Master SelectMAP and Slave SelectMAP
(or Slave Parallel) FPGA configuration modes. When the FPGA is in Master SelectMAP mode, the FPGA generates a
configuration clock that drives the PROM. When the FPGA is in Slave SelectMAP Mode, either an external oscillator
generates the configuration clock that drives the PROM and the FPGA, or optionally, the XQF32P PROM can be used to
drive the FPGA’s configuration clock. With BUSY Low and CF High, after CE and OE are enabled, data is available on the
PROM DATA (D0-D7) pins. New data is available a short access time after each rising clock edge. The data is clocked into
the FPGA on the following rising edge of the CCLK. A free-running oscillator can be used in the Slave Parallel /Slave
SelecMAP mode.
The XQF32P defense-grade version of the Platform Flash PROM provides additional advanced features. A built-in data
decompressor supports utilizing compressed PROM files, and design revisioning allows multiple design revisions to be
stored on a single PROM or stored across several PROMs. For design revisioning, external pins or internal control bits are
used to select the active design revision.
Multiple Platform Flash PROM devices can be cascaded to support the larger configuration files required when targeting
larger FPGA devices or targeting multiple FPGAs daisy chained together. When utilizing the advanced features for the
XQF32P Platform Flash PROM, such as design revisioning, programming files which span cascaded PROM devices can
only be created for cascaded chains containing only XQF32P PROMs.
The Platform Flash PROMs are compatible with all of the existing FPGA device families. The XQF32P Platform Flash PROM
capacity is 33,554,432 configuration bits.
DS541 (v3.0) August 5, 2015
Product Specification
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