DS541 Datasheet, PDF (15/27 Pages) Xilinx, Inc – Defense Grade Platform Flash In-System Programmable Configuration PROM

—PRODUCT OBSOLETE / UNDER OBSOLESCENCE—
Defense Grade Platform Flash In-System Programmable Configuration PROM
AC Electrical Characteristics
AC Characteristics Over Operating Conditions
XQF32P PROM as Configuration Slave with CLK Input Pin as Clock Source
X-Ref Target - Figure 6
CE
TSCE
OE/RESET
CLK
BUSY
(optional)
DATA
CF
TOE
TCE
TCF
THCF
TCYC
TLC
THC
TSB
TCAC
THB
TOH
THCE
THOE
TDF
TOH
EN_EXT_SEL
TSXT
THXT
TSXT
THXT
REV_SEL[1:0]
TSRV
THRV
TSRV
THRV
Figure 6: XQF32P PROM as Configuration Slave with CLK Input Pin as Clock Source
DS541_06_012011
Table 12: XQF32P PROM as Configuration Slave with CLK Input Pin as Clock Source
Symbol
Description
T_HCF
T_CF
T_OE
T_CE
T_CAC
T_OH
T_DF
CF hold time to guarantee design revision selection is sampled when V_CCO = 3.3V or 2.5V⁽⁹⁾
CF hold time to guarantee design revision selection is sampled when V_CCO = 1.8V⁽⁹⁾
CF to data delay when VCCO = 3.3V or 2.5V⁽⁸⁾
CF to data delay when VCCO = 1.8V⁽⁸⁾
OE/RESET to data delay⁽⁵⁾ when V_CCO = 3.3V or 2.5V
OE/RESET to data delay⁽⁵⁾ when V_CCO = 1.8V
CE to data delay⁽⁴⁾ when V_CCO = 3.3V or 2.5V
CE to data delay⁽⁴⁾ when V_CCO = 1.8V
CLK to data delay⁽⁷⁾ when V_CCO = 3.3V or 2.5V
CLK to data delay⁽⁷⁾ when V_CCO = 1.8V
Data hold from CE, OE/RESET, CLK, or CF when V_CCO = 3.3V or 2.5V⁽⁸⁾
Data hold from CE, OE/RESET, CLK, or CF when V_CCO = 1.8V⁽⁸⁾
CE or OE/RESET to data float delay⁽²⁾ when V_CCO = 3.3V or 2.5V
CE or OE/RESET to data float delay⁽²⁾ when V_CCO = 1.8V
XQF32P
Min
Max
300
–
300
–
–
25
–
25
–
30
–
30
–
30
–
30
–
30
–
30
5
–
5
–
–
45
–
45
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS541 (v3.0) August 5, 2015
Product Specification
www.xilinx.com
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