DS541 Datasheet, PDF (24/27 Pages) Xilinx, Inc – Defense Grade Platform Flash In-System Programmable Configuration PROM

—PRODUCT OBSOLETE / UNDER OBSOLESCENCE—
Defense Grade Platform Flash In-System Programmable Configuration PROM
Table 16: XQF32P Pin Names and Descriptions (VOG48) (Cont’d)
Pin Name
Boundary
Scan Order
Boundary
Scan
Function
Pin Description
CEO
06
Data Out Chip Enable Output. Chip Enable Output (CEO) is connected to the CE
input of the next PROM in the chain. This output is Low when CE is Low
05
Output Enable _{and OE/RESET input is High, AND the internal address counter has been}
incremented beyond its Terminal Count (TC) value. CEO returns to High
when OE/RESET goes Low or CE goes High.
EN_EXT_SEL
31
Data In
Enable External Selection Input. When this pin is Low, design revision
selection is controlled by the Revision Select pins. When this pin is High,
design revision selection is controlled by the internal programmable
Revision Select control bits. EN_EXT_SEL has an internal 50KΩ
resistive pull-up to V_CCO to provide a logic 1 to the device if the pin is not
driven.
REV_SEL0
30
REV_SEL1
29
BUSY
12
Data In
Data In
Data In
Revision Select[1:0] Inputs. When the EN_EXT_SEL is Low, the Revision
Select pins are used to select the design revision to be enabled,
overriding the internal programmable Revision Select control bits. The
Revision Select[1:0] inputs have an internal 50 KΩ resistive pull-up to
V_CCO to provide a logic 1 to the device if the pins are not driven.
Busy Input. The BUSY input is enabled when parallel mode is selected
for configuration. When BUSY is High, the internal address counter stops
incrementing and the current data remains on the data pins. On the first
rising edge of CLK after BUSY transitions from High to Low, the data for
the next address is driven on the data pins. When serial mode or
decompression is enabled during device programming, the BUSY input
is disabled. BUSY has an internal 50 KΩ resistive pull-down to GND to
provide a logic 0 to the device if the pin is not driven.
CLKOUT
TMS
08
Data Out Configuration Clock Output. An internal Programmable control bit
07
Output Enable
enables the CLKOUT signal, which is sourced from either the internal
oscillator or the CLK input pin. Each rising edge of the selected clock
source increments the internal address counter if data is available, CE is
Low, and OE/RESET is High. Output data is available on the rising edge
of CLKOUT. CLKOUT is disabled if CE is High or OE/RESET is Low. If
decompression is enabled, CLKOUT is parked High when decompressed
data is not ready. When CLKOUT is disabled, the CLKOUT pin is put into
a high-Z state. If CLKOUT is used, then it must be pulled High externally
using a 4.7 KΩ pull-up to V_CCO.
Mode Select
JTAG Mode Select Input. The state of TMS on the rising edge of TCK
determines the state transitions at the Test Access Port (TAP) controller.
TMS has an internal 50 KΩ resistive pull-up to V_CCJ to provide a logic 1
to the device if the pin is not driven.
TCK
Clock
JTAG Clock Input. This pin is the JTAG test clock. It sequences the TAP
controller and all the JTAG test and programming electronics.
TDI
Data In JTAG Serial Data Input. This pin is the serial input to all JTAG instruction
and data registers. TDI has an internal 50 KΩ resistive pull-up to V_CCJ to
provide a logic 1 to the device if the pin is not driven.
TDO
VCCINT
Data Out
JTAG Serial Data Output. This pin is the serial output for all JTAG
instruction and data registers. TDO has an internal 50KΩ resistive pull-up
to V_CCJ to provide a logic 1 to the system if the pin is not driven.
+1.8V Supply. Positive 1.8V supply voltage for internal logic.
VCCO
+3.3V, 2.5V, or 1.8V I/O Supply. Positive 3.3V, 2.5V, or 1.8V supply
voltage connected to the output voltage drivers and input buffers.
VCCJ
+3.3V or 2.5V JTAG I/O Supply. Positive 3.3V, 2.5V, or 1.8V supply
voltage connected to the TDO output voltage driver and TCK, TMS, and
TDI input buffers.
48-pin
TSOP
VOG48
10
25
26
27
5
9
21
20
19
22
4, 15, 34
8, 30,
38, 45
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DS541 (v3.0) August 5, 2015
Product Specification
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