DS541 Datasheet, PDF (8/27 Pages) Xilinx, Inc – Defense Grade Platform Flash In-System Programmable Configuration PROM

—PRODUCT OBSOLETE / UNDER OBSOLESCENCE—
Defense Grade Platform Flash In-System Programmable Configuration PROM
Design Revisioning
Design Revisioning allows the user to create up to four unique design revisions on a single PROM or stored across multiple
cascaded PROMs. Design Revisioning is supported for the XQF32P Platform Flash PROM in both serial and parallel
modes. Design Revisioning can be used with compressed PROM files, and also when the CLKOUT feature is enabled. The
PROM programming files along with the revision information files (.cfi) are created using the iMPACT software. The .cfi
file is required to enable design revision programming in iMPACT.
A single design revision is composed of from 1 to n 8-Mbit memory blocks. If a single design revision contains less than
8 Mbits of data, then the remaining space is padded with all ones. A larger design revision can span several 8-Mbit memory
blocks, and any space remaining in the last 8-Mbit memory block is padded with all ones.
• A single 32-Mbit PROM contains four 8-Mbit memory blocks, and can therefore store up to four separate design
revisions: one 32-Mbit design revision, two 16-Mbit design revisions, three 8-Mbit design revisions, four 8-Mbit design
revisions, and so on.
• Because of the 8-Mbit minimum size requirement for each revision, a single 16-Mbit PROM can only store up to two
separate design revisions: one 16-Mbit design revision, one 8-Mbit design revision, or two 8-Mbit design revisions.
• A single 8-Mbit PROM can store only one 8-Mbit design revision.
Larger design revisions can be split over several cascaded PROMs. For example, two 32-Mbit PROMs can store up to four
separate design revisions: one 64-Mbit design revision, two 32-Mbit design revisions, three 16-Mbit design revisions, four
16-Mbit design revisions, and so on.
See Figure 4 for a few basic examples of how multiple revisions can be stored. The design revision partitioning is handled
automatically during file generation in iMPACT.
During the PROM file creation, each design revision is assigned a revision number:
Revision 0 = 00
Revision 1 = 01
Revision 2 = 10
Revision 3 = 11
After programming the Platform Flash PROM with a set of design revisions, a particular design revision can be selected
using the external REV_SEL[1:0] pins or using the internal programmable design revision control bits. The EN_EXT_SEL
pin determines if the external pins or internal bits are used to select the design revision. When EN_EXT_SEL is Low, design
revision selection is controlled by the external Revision Select pins, REV_SEL[1:0]. When EN_EXT_SEL is High, design
revision selection is controlled by the internal programmable Revision Select control bits. During power up, the design
revision selection inputs (pins or control bits) are sampled internally. After power up, the design revision selection inputs are
sampled again when any of the following events occur:
• On the rising edge of CE
• On the falling edge of OE/RESET (when CE is Low)
• On the rising edge of CF (when CE is Low)
• When reconfiguration is initiated by using the JTAG CONFIG instruction.
The data from the selected design revision is then presented on the FPGA configuration interface.
DS541 (v3.0) August 5, 2015
Product Specification
www.xilinx.com
Send Feedback
8