DS541 Datasheet, PDF (22/27 Pages) Xilinx, Inc – Defense Grade Platform Flash In-System Programmable Configuration PROM

—PRODUCT OBSOLETE / UNDER OBSOLESCENCE—
Defense Grade Platform Flash In-System Programmable Configuration PROM
AC Characteristics Over Operating Conditions When Cascading
X-Ref Target - Figure 9
OE/RESET
CE
CLK
CLKOUT
(optional)
DATA
CEO
Last Bit
TCDF
TCODF
T_OCK
TCOCE
TOCE
TOOE
First Bit
DS541_17_111706
Figure 9: AC Characteristics Over Operating Conditions When Cascading
Table 15: AC Characteristics Over Operating Conditions When Cascading
Symbol
Description
T_CDF
T_OCK
T_OCE
T_OOE
T_COCE
T_CODF
CLK to output float delay⁽²⁾⁽³⁾ when V_CCO = 2.5V or 3.3V
CLK to output float delay⁽²⁾⁽³⁾ when V_CCO = 1.8V
CLK to CEO delay⁽³⁾⁽⁵⁾ when V_CCO = 2.5V or 3.3V
CLK to CEO delay⁽³⁾⁽⁵⁾ when V_CCO = 1.8V
CE to CEO delay⁽³⁾⁽⁶⁾ when V_CCO = 2.5V or 3.3V
CE to CEO delay⁽³⁾⁽⁶⁾ when V_CCO = 1.8V
OE/RESET to CEO delay⁽³⁾ when V_CCO = 2.5V or 3.3V
OE/RESET to CEO delay⁽³⁾ when V_CCO = 1.8V
CLKOUT to CEO delay when V_CCO = 2.5V or 3.3V
CLKOUT to CEO delay when V_CCO = 1.8V
CLKOUT to output float delay when V_CCO = 2.5V or 3.3V
CLKOUT to output float delay when V_CCO = 1.8V
XQF32P
Min
Max
–
25
–
25
–
20
–
20
–
80
–
80
–
80
–
80
–
25
–
25
–
30
–
30
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. AC test load = 30 pF for XQF32P.
2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with V_IL = 0.0V and V_IH = 3.0V.
5. For cascaded PROMs, if the FPGA’s dual-purpose configuration data pins are set to persist as configuration pins, the minimum
period is increased based on the CLK to CEO and CE to data propagation delays:
- T_CYC minimum = T_OCK + T_CE + FPGA Data setup time.
- T_CAC maximum = T_OCK + T_CE
6. For cascaded PROMs, if the FPGA’s dual-purpose configuration data pins become general I/O pins after configuration; to allow for
the disable to propagate to the cascaded PROMs and to avoid contention on the data lines following configuration, the minimum
period is increased based on the CE to CEO and CE to data propagation delays:
- T_CYC minimum = T_OCE + T_CE
- T_CAC maximum = T_OCK + T_CE
DS541 (v3.0) August 5, 2015
Product Specification
www.xilinx.com
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