DS541 Datasheet, PDF (7/27 Pages) Xilinx, Inc – Defense Grade Platform Flash In-System Programmable Configuration PROM

—PRODUCT OBSOLETE / UNDER OBSOLESCENCE—
Defense Grade Platform Flash In-System Programmable Configuration PROM
Additional Features for the XQF32P
Internal Oscillator
The 32-Mbit XQF32P Platform Flash PROMs include an optional internal oscillator which can be used to drive the CLKOUT
and DATA pins on FPGA configuration interface. The internal oscillator can be enabled when programming the PROM, and
the oscillator can be set to either the default frequency or to a slower frequency (XQF32P PROM as Configuration Master
with Internal Oscillator as Clock Source, page 19).
CLKOUT
The 32-Mbit XQF32P Platform Flash PROMs include the programmable option to enable the CLKOUT signal which allows
the PROM to provide a source synchronous clock aligned to the data on the configuration interface. The CLKOUT signal is
derived from one of two clock sources: the CLK input pin or the internal oscillator. The input clock source is selected during
the PROM programming sequence. Output data is available on the rising edge of CLKOUT.
The CLKOUT signal is enabled during programming, and is active when CE is Low and OE/RESET is High. On CE rising
edge transition, if OE/RESET is High and the PROM terminal count has not been reached, then CLKOUT remains active for
an additional eights clock cycles before being disabled. On a OE/RESET falling edge transition, CLKOUT is immediately
disabled. When disabled, the CLKOUT pin is put into a high-impedance state and should be pulled High externally to provide
a known state.
When cascading Platform Flash PROMs with CLKOUT enabled, after completing it's data transfer, the first PROM disables
CLKOUT and drives the CEO pin enabling the next PROM in the PROM chain. The next PROM begins driving the CLKOUT
signal once that PROM is enabled and data is available for transfer.
During high-speed parallel configuration without compression, the FPGA drives the BUSY signal on the configuration
interface. When BUSY is asserted High, the PROMs internal address counter stops incrementing, and the current data
value is held on the data outputs. While BUSY is High, the PROM continues driving the CLKOUT signal to the FPGA,
clocking the FPGA’s configuration logic. When the FPGA deasserts BUSY, indicating that it is ready to receive additional
configuration data, the PROM begins driving new data onto the configuration interface.
Decompression
The 32-Mbit XQF32P Platform Flash PROMs include a built-in data decompressor compatible with Xilinx advanced
compression technology. Compressed Platform Flash PROM files are created from the target FPGA bitstream(s) using the
iMPACT software. Only Slave Serial and Slave SelectMAP (parallel) configuration modes are supported for FPGA
configuration when using a XQF32P PROM programmed with a compressed bitstream. Compression rates vary depending
on several factors, including the target device family and the target design contents.
The decompression option is enabled during the PROM programming sequence. The PROM decompresses the stored data
before driving both clock and data onto the FPGA's configuration interface. If Decompression is enabled, then the Platform
Flash clock output pin (CLKOUT) must be used as the clock signal for the configuration interface, driving the target FPGA's
configuration clock input pin (CCLK). Either the PROM's CLK input pin or the internal oscillator must be selected as the
source for CLKOUT. Any target FPGA connected to the PROM must operate as slave in the configuration chain, with the
configuration mode set to Slave Serial mode or Slave SelectMap (parallel) mode.
When decompression is enabled, the CLKOUT signal becomes a controlled clock output with a reduced maximum
frequency. When decompressed data is not ready, the CLKOUT pin is put into a high-Z state and must be pulled High
externally to provide a known state.
The BUSY input is automatically disabled when decompression is enabled.
DS541 (v3.0) August 5, 2015
Product Specification
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