DS541 Datasheet, PDF (5/27 Pages) Xilinx, Inc – Defense Grade Platform Flash In-System Programmable Configuration PROM

—PRODUCT OBSOLETE / UNDER OBSOLESCENCE—
Defense Grade Platform Flash In-System Programmable Configuration PROM
Instruction Register
The Instruction Register (IR) for the Platform Flash PROM is connected between TDI and TDO during an instruction scan
sequence. In preparation for an instruction scan sequence, the instruction register is parallel loaded with a fixed instruction
capture pattern. This pattern is shifted out onto TDO (LSB first), while an instruction is shifted into the instruction register
from TDI.
XQF32P Instruction Register (16 bits wide)
The Instruction Register (IR) for the XQF32P PROM is sixteen bits wide and is connected between TDI and TDO during an
instruction scan sequence. The detailed composition of the instruction capture pattern is illustrated in Table 4.
The instruction capture pattern shifted out of the XQF32P device includes IR[15:0]. IR[15:9] are reserved bits and are set to
a logic 0. The ISC Error field, IR[8:7], contains a 10 when an ISC operation is a success; otherwise a 01 when an In-System
Configuration (ISC) operation fails. The Erase/Program (ER/PROG) Error field, IR[6:5], contains a 10 when an erase or
program operation is a success; otherwise a 01 when an erase or program operation fails. The Erase/Program (ER/PROG)
Status field, IR[4], contains a logic 0 when the device is busy performing an erase or programming operation; otherwise, it
contains a logic 1. The ISC Status field, IR[3], contains logic 1 if the device is currently in In-System Configuration (ISC)
mode; otherwise, it contains logic 0. The DONE field, IR[2], contains logic 1 if the sampled design revision has been
successfully programmed; otherwise, a logic 0 indicates incomplete programming. The remaining bits IR[1:0] are set to 01
as defined by IEEE Std. 1149.1.
Table 4: XQF32P Instruction Capture Values Loaded into IR as part of an Instruction Scan Sequence
TDI →
IR[15:9]
Reserved
IR[8:7]
ISC Error
IR[6:5]
ER/PROG
Error
IR[4]
ER/PROG
Status
IR[3]
ISC Status
IR[2]
DONE
IR[1:0]
01
→ TDO
Boundary Scan Register
The boundary-scan register is used to control and observe the state of the device pins during the EXTEST, SAMPLE/PRELOAD,
and CLAMP instructions. Each output pin on the Platform Flash PROM has two register stages which contribute to the
boundary-scan register, while each input pin has only one register stage. The bidirectional pins have a total of three register stages
which contribute to the boundary-scan register. For each output pin, the register stage nearest to TDI controls and observes the
output state, and the second stage closest to TDO controls and observes the High-Z enable state of the output pin. For each input
pin, a single register stage controls and observes the input state of the pin. The bidirectional pin combines the three bits, the input
stage bit is first, followed by the output stage bit and finally the output enable stage bit. The output enable stage bit is closest to
TDO.
See the XQF32P Pin Names and Descriptions Tables in Pinouts and Pin Descriptions, page 23 for the boundary-scan bit order for
all connected device pins, or see the appropriate BSDL file for the complete boundary-scan bit order description under the
attribute BOUNDARY_REGISTER section in the BSDL file. The bit assigned to boundary-scan cell 0 is the LSB in the
boundary-scan register, and is the register bit closest to TDO.
Identification Registers
IDCODE Register
The IDCODE is a fixed, vendor-assigned value that is used to electrically identify the manufacturer and type of the device being
addressed. The IDCODE register is 32 bits wide. The IDCODE register can be shifted out for examination by using the
IDCODE instruction. The IDCODE is available to any other system component via JTAG.
The IDCODE register has the following binary format:
vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1
where:
v = the die version number
f = the PROM family code
a = the specific Platform Flash PROM product ID
c = the Xilinx manufacturer's ID
The LSB of the IDCODE register is always read as logic 1 as defined by IEEE Std. 1149.1. The IDCODE register value for
the XQ32PPlatform Flash PROM is <v>5059093.
Note: The <v> in the IDCODE field represents the device’s revision code (in hex) and can vary.
DS541 (v3.0) August 5, 2015
Product Specification
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