DS620 Datasheet, PDF (8/30 Pages) Dallas Semiconductor – Low-Voltage, +-0.5°C Accuracy Digital Thermometer and Thermostat

LogiCORE IP XPS SYSMON ADC (v3.00.b)
Table 2: I/O Signal Descriptions (Cont’d)
Port
Signal Name
Interface I/O
Initial
State
XPS SYSMON ADC IP Core Interface Signals
P44 VAUXP[15 : 0]
SYSMON
I
-
P45 VAUXN[15 : 0]
SYSMON
I
-
P46 CONVST
SYSMON
I
-
P47 ALARM[2:0]
SYSMON O
0
Description
Positive auxiliary differential
analog inputs
Negative auxiliary differential
analog inputs
Convert Start input port is used to
control the sampling instant on the
ADC input and is used only in
event-driven sampling mode. This
port is auto connected to ground
internally, if not in use.
SYSMON hard macro Alarm
output signals
Parameter - Port Dependencies
The dependencies between the XPS SYSMON ADC IP core design parameters and I/O signals are described in
Table 3.
Table 3: Parameter-Port Dependencies
Generic
or Port
Name
Affects Depends
Relationship Description
Design Parameters
G5 C_SPLB_DWIDTH
P8, P11,
P34
-
Affects the number of bits in data bus
G7 C_SPLB_MID_WIDTH
This value is calculated as:
P6
G8
log₂(C_SPLB_NUM_MASTERS) with
a minimum value of 1
G8 C_SPLB_NUM_MASTERS
P37, P38,
P39, P43
-
Affects the number of PLB masters
I/O Signals
P6 PLB_masterID[0 : C_SPLB_MID_WIDTH - 1]
-
G7
Width of the PLB_mastedID varies
according to C_SPLB_MID_WIDTH
P8 PLB_BE[0 : (C_SPLB_DWIDTH/8) -1]
-
G5
Width of the PLB_BE varies according
to C_SPLB_DWIDTH
P11 PLB_wrDBus[0 : C_SPLB_DWIDTH - 1]
-
G5
Width of the PLB_wrDBus varies
according to C_SPLB_DWIDTH
P34 Sl_rdDBus[0 : C_SPLB_DWIDTH - 1]
-
G5
Width of the Sl_rdDBus varies
according to C_SPLB_DWIDTH
P37 Sl_MBusy[0 : C_SPLB_NUM_MASTERS - 1]
-
Width of the Sl_MBusy varies
G8
according to
C_SPLB_NUM_MASTERS
P38 Sl_MWrErr[0 : C_SPLB_NUM_MASTERS - 1]
-
Width of the Sl_MWrErr varies
G8
according to
C_SPLB_NUM_MASTERS
DS620 October 19, 2011
www.xilinx.com
8
Product Specification