DS620 Datasheet, PDF (25/30 Pages) Dallas Semiconductor – Low-Voltage, +-0.5°C Accuracy Digital Thermometer and Thermostat

LogiCORE IP XPS SYSMON ADC (v3.00.b)
Continuous Cycling Of Sequence Mode Example
To configure the XPS SYSMON ADC IP core in the Continuous Cycling of Sequence Mode, the SEQ1 and SEQ0 bits
in the Configuration Register 1 should be set to ’1’ and ’0’, respectively. The specific value written to registers can
vary depending upon the need of the application. Following is the configuration example for monitoring the
On-Chip Temperature channels, V_CCINT and V_CCAUX, in a continuous cycling of sequence mode with the clock ratio
set to 32.
1. Issue a software reset by writing the data word 0x0000_000A to the SRR. This asserts the reset of the XPS
SYSMON ADC IP core for 16 clock cycles.
2. Write 0x0000_0000 to Configuration register 0. This configures the SYSMON hard macro in continuous
sampling mode.
3. Write 0x0000_2000 to Configuration register 1. This configures the SYSMON hard macro in continuous cycling
of sequence mode, all calibration disabled and all alarm outputs enabled.
4. Write 0x0000_2000 to Configuration Register 2. This configures the SYSMON hard macro to have ADCCLK =
DCLK/32.
5. Read Status Register (SR) to reset EOC/EOS signal set by any previous conversions.
6. If an interrupt controller is present, then read IPISR to know the value set by any previous conversions. Assume
for this application the value read is 0x0000_003E.
7. Write 0x0000_003E to IPISR to toggle the bits which are ’1’ so that the new value of IPISR becomes 0x0000_0000.
8. If interrupt controller is present, that is, C_INCLUDE_INTR = 1, do global enabling of interrupts by writing
0x8000_0000 to GIER.
9. Enable the operational interrupts by writing 0x0000_00FF to the IPIER.
10. Write 0x0000_0700 to Sequence Register 0 and 0x0000_0000 to Sequence Register 1. This configures SYSMON
hard macro for monitoring On-Chip Temperature, V_CCINT and V_CCAUX channel.
11. Write 0x0000_0000 to Sequence Register 2 and 3. This disables ADC channel averaging.
12. Write 0x0000_0000 to Sequence Register 4 and 5. This configures ADC channel in unipolar input mode.
13. Write 0x0000_0000 to Sequence Register 6 and 7. This configures ADC channel acquisition time to four
ADCCLK cycles.
14. Write 0x0000_A900 to Alarm Register 0. This configures the upper limit for temperature alarm, which for this
application is set to 60^o C.
15. Write 0x0000_9980 to Alarm Register 1. This configures the upper limit for V_CCINT alarm, which for this
application is set to 1.8 V.
16. Write 0x0000_EE80 to Alarm Register 2. This configures the upper limit for V_CCAUX alarm, which for this
application is set to 2.8 V.
17. Write 0x0000_A000 to Alarm Register 4. This configures the lower limit for temperature alarm, which for this
application is set to 42^o C.
18. Write 0x0000_4400 to Alarm Register 5. This configures the lower limit for V_CCINT alarm, which for this
application is set to 0.8 V.
19. Write 0x0000_9980 to Alarm Register 6. This configures the lower limit for V_CCAUX alarm, which for this
application is set to 1.8 V.
20. Write 0x0000_A180 to Alarm Register 7. This configures the lower limit for OT alarm, which for this application
is set to 45^o C.
21. The Alarm Register 3 is active only in case of Virtex-6 device. When the Virtex-6 FPGA is targeted then this
register is used to set the upper limit of OT. The OT upper is 12 bit register, with lower 4 bits needs to be set to
"0011". If this register is left un-initialized, then 125^o C is considered as the default upper temperature for OT.
DS620 October 19, 2011
www.xilinx.com
25
Product Specification