DS620 Datasheet, PDF (3/30 Pages) Dallas Semiconductor – Low-Voltage, +-0.5°C Accuracy Digital Thermometer and Thermostat

LogiCORE IP XPS SYSMON ADC (v3.00.b)
The XPS SYSMON ADC IP core consists of following major blocks.
• PLB Interface Module
• SYSMON ADC Core Logic
• SYSMON Hard Macro
PLB Interface Module
The PLB Interface Module provides the interface to the PLB. Read and write transactions at the PLB are translated
into equivalent SYSMON ADC core logic and SYSMON hard macro transactions. The register interfaces of the
SYSMON ADC core Logic Module connect to the PLB Interface Module. The PLB Interface Module also provides an
address decoding service.
SYSMON ADC Core Logic
The SYSMON ADC core Logic Module provides necessary address decoding logic, control signal generation and
interface between the PLB and the SYSMON hard macro. The read/write requests along with the address and data
(in case of write) from the PLB Interface Module are transferred to either the Dynamic Reconfiguration Port (DRP)
registers of the SYSMON hard macro or local registers in the IP along with the necessary control signals, such as
DEN and DWE.
If the SYSMON ADC Core Logic Module supports including/excluding the Interrupt Controller based on generic
C_INCLUDE_INTR. If C_INCLUDE_INTR = 1, then the Interrupt Controller is included in the design.
There is a new Design Rule Checker (DRC) limitation which has been imposed on the DCLK input clock of
SYSMON hard macro on Virtex-6 devices. The DCLK for the hard macro must not exceed 80 Mega Hertz (MHz)
value. To take care of this limitation a new parameter ‘C_DCLK_RATIO’ is added in the design. Based upon the core
frequency (when used in the system), this parameter needs to be set in such a way as to make the DCLK less than
or equal to 80 MHz. These constraints are applicable only for the Virtex-6 device. Users must make sure that the
maximum clock at this port is 80 MHz. If this clock increases beyond 80 MHz, then a DRC violation related to the
SYSMON hard macro will be raised and the hard macro may not work properly. For all Virtex-5 devices, this
parameter should be assigned to ‘1’. In short, the SYSMON hard macro on Virtex-5 devices can operate at the core
frequency which can be beyond 80 MHz.
The C_DCLK_RATIO supports a range of values between 1 to 8. Internally, this value is used to divide the clock. It
is strongly recommended that the value of C_DCLK_RATIO should be set in such a way that, the DCLK input
frequency is always equal to 80 MHz or close to 80 MHz. Read Precautions to be taken while Assigning the C_DCLK_RATIO
Parameter.
The SYSMON hard macro can be accessed via both Joint Test Action Group (JTAG) TAP (Test Access Port) and the
XPS SYSMON ADC IP core. When simultaneous access of the SYSMON hard macro occurs, the JTAGLOCKED port
can be asserted High by JTAG TAP. In this scenario, the XPS SYSMON ADC IP Core is not allowed to do any
read/write access from/to DRP. When the JTAGLOCKED port is again deasserted through JTAG TAP, the XPS
SYSMON ADC IP core can perform a read/write operation from/to DRP.
This functionality is especially useful in applications where the user is configuring DRP through JTAG TAP and
does not want the FPGA logic (XPS SYSMON ADC IP core) to alter the configuration. The user can make
JTAGLOCKED = ’1’ through JTAG TAP, which blocks any read and write transactions from or to DRP through the
FPGA logic and thus ensures a non-destructive access through the JTAG TAP.SYSMON Hard Macro
The SYSMON hard macro is present in every Virtex-5 and Virtex-6 FPGA. The block diagram for the System
Monitor ADC hard macro on a Virtex-5 FPGA is shown in Figure 2.
DS620 October 19, 2011
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Product Specification