DS620 Datasheet, PDF (13/30 Pages) Dallas Semiconductor – Low-Voltage, +-0.5°C Accuracy Digital Thermometer and Thermostat

LogiCORE IP XPS SYSMON ADC (v3.00.b)
Table 4: Core Registers (Cont’d)
Base Address + Offset
(hex)
Register Name
C_BASEADDR + 0x360 to
C_BASEADDR + 0x3FC
Undefined
Access Type
Default
Value (hex)
Description
N/A
Undefined Do not Read/Write these register
Notes:
1. Reading of this register returns an undefined value.
2. Writing into this register has no effect.
3. Used in event-driven sampling mode only.
4. TOW = Toggle On Write. Writing a ’1’ to a bit position within the register causes the corresponding bit position in the register to
toggle.
5. These are 16-bit registers internal to the SYMON hard macro. These are mapped to the lower half word boundary on the 32-bit
XPS SYMON ADC IP core registers. For more detail See the System Monitor Register File Interface section in the Virtex-5 and
Virtex-6 System Monitor User Guide,UG192 (latest version).
6. Writing to this SYSMON hard macro register is not allowed. The SYSMON ADC hard macro data registers are 16-bits in width. The
SYSMON hard macro specification guarantees the first 10-MSB bits accuracy, so only these bits are used for reference.
7. Writing to this register resets the SYSMON hard macro. No specific data pattern is required to reset the SYSMON hard macro.
Reading of this register gives the details of Vp/Vn port.
8. See the System Monitor User Guide, UG192 (latest version) for setting the different bits available in configuration registers for
Virtex-5 and Virtex-6 devices.
9. The OT upper register is available only in Virtex-6 FPGAs. This register location is N/A when Virtex-5 devices are targeted.
10. The OT upper register is a user-configurable register for the upper threshold level of temperature. If this register is left
unconfigured, then the SYSMON considers 125⁰C as the upper threshold value for OT. Note that, while configuring this register,
the last 4-bits must be set to 0011 Alarm Threshold Register 3[3:0] = 0011. The upper 12 bits of this register are user configurable.
Local Register Grouping
It is expected that the XPS SYSMON ADC IP core registers are going to be accessed in their preferred-access mode
only. If the write attempt is made to read-only registers, there is not any effect on register contents. If the write-only
registers are read, then it results in undefined data. All the internal registers of the core must be accessed in 32-bit
format. If any other kind of access, such as half word or byte access, is done for the XPS SYSMON ADC IP core’s
internal 32 bit registers, the transaction is completed with an error generation for the corresponding transaction.
Software Reset Register (SRR)
The Software Reset Register permits the programmer to reset the XPS SYSMON ADC IP core, including the
SYSMON hard macro output ports (except JTAG related outputs), independently of other IP cores in the systems.
To activate the software reset, the value 0x0000_000A must be written to the register. Any other access, read or write,
has undefined results. The bit assignment in the software reset register is shown in Figure 3 and described in
Table 5.
X-Ref Target - Figure 3
0
31
Reset
Figure 3: Software Reset Register
DS620_02_020509
Table 5: Software Reset Register Description (C_BASEADDR + 0x00)
Bit(s) Name
Core
Access
Reset
Value
Description
0 - 31
Reset
Write only
The only allowed operation on this register is a write of 0x0000_000A, which
N/A resets the XPS SYSMON ADC IP Core. The reset is active only for two clock
cycles.
DS620 October 19, 2011
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Product Specification