DS620 Datasheet, PDF (26/30 Pages) Dallas Semiconductor – Low-Voltage, +-0.5°C Accuracy Digital Thermometer and Thermostat

LogiCORE IP XPS SYSMON ADC (v3.00.b)
22. Write 0x0000_2000 to Configuration Register 1. This configures the SYSMON hard macro in continuous cycling
of sequence mode, all calibration disabled and all alarm outputs enabled. We need to perform a write operation
on this register to enable the sequence written to sequence registers. [See the System Monitor User Guide for
bits of Configuration Register 0, when targeted for Virtex-5 and Virtex-6 devices]
23. Read SR, if the present conversion cycle is completed then EOS bit in SR is set to ’1’. If the interrupt controller
is present then the EOS bit in IPISR is also set to ’1’.
24. Read converted value of On-Chip Temperature, V_CCINT and V_CCAUX channel from address C_BASEADDR +
0x200, C_BASEADDR + 0x204 and C_BASEADDR + 0x208 respectively.
Single Channel Mode Examples
To configure the XPS SYSMON ADC IP core in Single Channel Mode, both the SEQ1 and SEQ0 bits in the
Configuration register 1 should be set to ’1’. The Single Channel Operation can be programmed to operate either in
Event-Driven Sampling Mode or Continuous Sampling Mode by setting the EC bit in Configuration Register 0 to ’1’
or ’0’.
Single Channel Event-Driven Sampling Mode Example
To configure the XPS SYSMON ADC IP core in Single Channel Event-Driven Sampling Mode, EC bit in
Configuration Register 0 should be set to ’1’. The specific value written to registers can vary depending upon the
need of the application. Also if On-Chip temperature or voltages are monitored, then the Alarm registers should be
configured with the appropriate values before writing to the Configuration Registers. Following is the
configuration example for monitoring the V_P/V_N channel with the clock ratio set to 32.
1. Issue a software reset by writing the data word 0x0000_000A to the SRR. This asserts the reset of the XPS
SYSMON ADC IP core for 16 clock cycles.
2. If interrupt controller is present, for example, C_INCLUDE_INTR = 1, perform the global enabling of interrupts
by writing 0x8000_0000 to the GIER register.
3. Enable the operational interrupts by writing 0x0000_00FF to the IPIER register.
4. Write 0x0000_0203 to Configuration register 0. This configures the SYSMON hard macro with no averaging,
unipolar mode, event-driven sampling, and selects channel 3 (V_P/V_N) for conversion.
5. Write 0x0000_3000 to Configuration register 1. This configures the SYSMON hard macro in single channel
mode, all calibration disabled and all alarm outputs enabled.
6. Write 0x0000_2000 to Configuration register 2. This configures the SYSMON hard macro to have ADCCLK =
DCLK/32.
7. Read the Status Register (SR) to reset the EOC/EOS signal which has been set by any previous conversions.
8. If interrupt controller is present, read the IPISR register to know the value set by any previous conversions.
Assume for this application the value read is 0x0000_003E.
9. Write 0x0000_003E to IPISR to toggle the bits which are ’1’ so that the new value of IPISR becomes 0x0000_0000.
10. Conversion Start can be signalled by writing 0x0000_0001 to CONVSTR or by making external CONVST port =
’1’.
11. Reset the CONVSTR by writing 0x0000_0000 to it or by making CONVST port = ’0’ depending upon which
kind of trigger (either CONVSTR register or CONVST port) is used for the conversion start.
12. Read SR, if conversion is completed then the EOC bit in SR is set to ’1’. If the interrupt controller is present then
EOC bit in the IPISR is also set to ’1’.
13. Read converted value of channel 3 (V_P/V_N) from address C_BASEADDR + 0x20C.
DS620 October 19, 2011
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Product Specification