DS620 Datasheet, PDF (15/30 Pages) Dallas Semiconductor – Low-Voltage, +-0.5°C Accuracy Digital Thermometer and Thermostat

LogiCORE IP XPS SYSMON ADC (v3.00.b)
Alarm Output Status Register (AOSR)
The Alarm Output Status Register contains all the alarm outputs for the XPS SYSMON ADC IP core. This register
is read only. Any attempt to write the bits of the register does not change the bits. The Alarm Output Status Register
bit definitions are shown in Figure 5 and explained in Table 7.
X-Ref Target - Figure 5
Undefined
ALM[1] OT
0
27 28 29 30 31
Figure 5: Alarm Output Status Register
ALM[2] ALM[0]
DS620_05_020509
Table 7: Alarm Output Status Register (C_BASEADDR + 0x08)
Bit(s) Name
Core
Access
Reset
Value
Description
0 - 27 Undefined
N/A
N/A Undefined
28
ALM[2]
Read
System Monitor VCCAUX-sensor Interrupt. System Monitor VCCAUX-sensor
’0’ alarm output interrupt occurs when VCCAUX exceeds user-defined
threshold.
29
ALM[1]
Read
’0’
System Monitor VCCINT-sensor Interrupt. System Monitor VCCINT-sensor
alarm output interrupt occurs when VCCINT exceeds user-defined threshold.
30
ALM[0]
Read
System Monitor temperature-sensor Interrupt. System Monitor
’0’ temperature-sensor alarm output interrupt occurs when device temperature
exceeds user-defined threshold.
31
OT
Read
Over-Temperature alarm Interrupt. Over-Temperature alarm output interrupt
’0’ occurs when the die temperature exceeds a factory set limit of 125 degree
celsius.
CONVST Register (CONVSTR)
The CONVST Register is used for initiating a new conversion in the event-driven sampling mode. The output of
this register is logically ORed with an external CONVST input signal. The attempt to read this register results in
undefined data. The CONVST Register bit definitions are shown in Figure 6 and explained in Table 8.
X-Ref Target - Figure 6
Undefined
CONVST
0
30 31
DS620_06_020509
Figure 6: CONVST Register
Table 8: CONVST Register (C_BASEADDR + 0x0C)
Bit(s) Name
Core
Access
Reset
Value
Description
0 - 30 Undefined
N/A
N/A Undefined
31 CONVST
Write
A rising edge on the CONVST input initiates start of ADC conversion in
’0’
event-driven sampling mode. For selected channel the CONVST bit in the
register needs to be set to ’1’ and again reset to ’0’ to start a new conversion
cycle. The conversion cycle ends with EOC bit going high.
DS620 October 19, 2011
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Product Specification