DS620 Datasheet, PDF (16/30 Pages) Dallas Semiconductor – Low-Voltage, +-0.5°C Accuracy Digital Thermometer and Thermostat

LogiCORE IP XPS SYSMON ADC (v3.00.b)
SYSMON Reset Register (SYSMONRR)
The SYSMON Reset Register is used to reset only the SYSMON hard macro. As soon as the reset is released, the
ADC begins with a new conversion. If sequencing is enabled, this conversion is the first in the sequence. This
register resets the OT and ALM[n] output from the SYSMON hard macro. This register does not reset the interrupt
registers if they are included in the design. Also any reset from the FPGA logic does not affect the RFI (Register File
Interface) contents of the SYSMON hard macro. The attempt to read this register results in undefined data. The
SYSMON Reset Register bit definitions are shown in Figure 7 and explained in Table 9.
X-Ref Target - Figure 7
Undefined
SYSMON
Reset
0
30 31
DS620_07_020509
Figure 7: SYSMON Reset Register
Table 9: SYSMON Reset Register (C_BASEADDR + 0x10)
Bit(s) Name
Core
Access
Reset
Value
Description
0 - 30 Undefined
N/A
N/A Undefined.
31
SYSMON
Reset
Write
’0’
Writing ’1’ to this bit position resets the SYSMON hard macro. The reset is
released only after ’0’ is written to this register.
XPS SYSMON ADC Interrupt Controller Register Grouping
The Interrupt Controller Module is included in XPS SYSMON ADC IP core design when C_INCLUDE_INTR = ’1’.
The XPS SYSMON ADC has a number of distinct interrupts that are sent to the Interrupt Controller Module which
is one of the submodules of the XPS SYSMON ADC IP core. The Interrupt Controller Module allows each interrupt
to be enabled independently (via the IP interrupt enable register (IPIER)). All the interrupt signals are rising edge
sensitive.
The interrupt registers are in the Interrupt Controller Module. The XPS SYSMON ADC IP core permits multiple
conditions for an interrupt, or an interrupt strobe which occurs only after the completion of a transfer.
Global Interrupt Enable Register (GIER)
The Global Interrupt Enable Register (GIER) is used to globally enable the final interrupt output from the Interrupt
Controller as shown in Figure 8 and described in Table 10. This bit is a read/write bit and is cleared upon reset.
X-Ref Target - Figure 8
GIER
Undefined
01
Figure 8: Global Interrupt Enable Register (GIER)
31
DS620_08_020509
DS620 October 19, 2011
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