DS620 Datasheet, PDF (17/30 Pages) Dallas Semiconductor – Low-Voltage, +-0.5°C Accuracy Digital Thermometer and Thermostat

LogiCORE IP XPS SYSMON ADC (v3.00.b)
Table 10: Global Interrupt Enable Register (GIER) Description (C_BASEADDR + 0x5C)
Bit(s)
Name
Access
Reset
Value
Description
Global Interrupt Enable Register. It enables all individually enabled interrupts
0
GIER
R/W
’0’
to be passed to the interrupt controller.
’0’ = Disabled
’1’ = Enabled
1 - 31 Undefined N/A
N/A Undefined.
IP Interrupt Status Register (IPISR)
Six unique interrupt conditions are possible in the XPS SYSMON ADC IP core.
The Interrupt Controller has a register that can enable each interrupt independently. Bit assignment in the Interrupt
register for a 32-bit data bus is shown in Figure 9 and described in Table 11. The interrupt register is a read/toggle
on write register and by writing a ’1’ to a bit position within the register causes the corresponding bit position in the
register to ’toggle’. All register bits are cleared upon reset.
X-Ref Target - Figure 9
Undefined
JTAG
LOCKED EOS ALM[1] ^OT
0
23 24 25 26 27 28 29 30 31
JTAG EOC ALM[2] ALM[0]
MODIFIED
DS620_09_020509
Figure 9: IP Interrupt Status Register (IPISR)
DS620 October 19, 2011
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Product Specification