DS620 Datasheet, PDF (27/30 Pages) Dallas Semiconductor – Low-Voltage, +-0.5°C Accuracy Digital Thermometer and Thermostat

LogiCORE IP XPS SYSMON ADC (v3.00.b)
Single Channel Continuous Sampling Mode Example
To configure the XPS SYSMON ADC IP core in the Single Channel Continuous Sampling Mode, the EC bit in
Configuration Register 0 should be set to ’0’. The specific value written to registers can vary depending upon the
need of the application. Also, if On-Chip temperature or voltages are monitored, then the Alarm registers should be
configured with appropriate values before writing to Configuration Registers. Following is the configuration
example for monitoring V_P/V_N channel with clock ratio set to 32.
1. Issue a software reset by writing the data word 0x0000_000A to the SRR. This asserts the reset of the XPS
SYSMON ADC IP core for 16 clock cycles.
2. If interrupt controller is present, that is, C_INCLUDE_INTR = 1, do global enabling of interrupts by writing
0x8000_0000 to GIER.
3. Enable the operational interrupts by writing 0x0000_00FF to the IPIER.
4. Write 0x0000_0003 to Configuration Register 0. This configures the SYSMON hard macro with no averaging,
unipolar mode, event-driven sampling, and selects channel 3 (V_P/V_N) for conversion.
5. Write 0x0000_3000 to Configuration Register 1. This configures the SYSMON hard macro in single channel
mode, all calibration disabled and all alarm outputs enabled.
6. Write 0x0000_2000 to Configuration Register 2. This configures the SYSMON hard macro to have ADCCLK =
DCLK/32.
7. Write 0x0000_0001 to the SYSMON Reset Register to reset the SYSMON hard macro. This step is required to put
the SYSMON hard macro in the reset state.
8. Read Status Register (SR) to reset EOC/EOS signal set by any previous conversions. After reading the Status
Register the EOC, EOS from IP core is in reset state.
9. If Interrupt Controller is present, read IPISR to know the value set by any previous conversions. Assume for this
application the value read is 0x0000_003E.
10. Write 0x0000_003E to IPISR to toggle the bits which are ’1’ so that the new value of IPISR becomes 0x0000_0000.
11. Write 0x0000_0000 to the SYSMON Reset Register to bring the SYSMON hard macro out of reset. After the
SYSMON hard macro comes out of reset, it starts its normal operation of data acquisition of the configured
channels.
12. Read SR, if conversion is completed then the EOC bit in SR is set to ’1’. If the interrupt controller is present, the
EOC bit in IPISR is also set to ’1’.
13. Read converted value of channel 3 (V_P/V_N) from address C_BASEADDR + 0x20C.
Reference Documents
To search for Xilinx documentation, go to http://www.xilinx.com/support.
1. UG192 Virtex-5 FPGA System Monitor User Guide
2. UG370 Virtex-6 FPGA System Monitor User Guide
3. DS561 PLBV46 Slave Single Product Specification
4. IBM CoreConnect^™128-Bit Processor Local Bus, Architectural Specification (v4.6)
Support
Xilinx provides technical support for this LogiCORE™ product when used as described in the product documenta-
tion. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices that are not
defined in the documentation, if customized beyond that allowed in the product documentation, or if changes are
made to any section of the design labeled DO NOT MODIFY.
DS620 October 19, 2011
www.xilinx.com
27
Product Specification