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DS620 Datasheet, PDF (14/30 Pages) Dallas Semiconductor – Low-Voltage, +-0.5°C Accuracy Digital Thermometer and Thermostat
LogiCORE IP XPS SYSMON ADC (v3.00.b)
Status Register (SR)
The Status Register contains the XPS SYSMON ADC IP core channel status and the End of Conversion (EOC), End
of Sequence (EOS), and JTAG access signals. This register is read only. Any attempt to write the bits of the register
does not change the bits. The Status Register bit definitions are shown in Figure 4 and explained in Table 6.
X-Ref Target - Figure 4
Undefined
JTAG
LOCKED
JTAGBUSY
EOS
CH4
CH2
CH0
0
20 21 22 23 24 25 26 27 28 29 30 31
JTAG BUSY EOC
MODIFIED
Figure 4: Status Register
CH3 CH1
DS620_04_020509
Table 6: Status Register (C_BASEADDR + 0x04)
Bit(s)
Name
Core
Access
Reset
Value
Description
0 - 20 Undefined
N/A
N/A Undefined
21 JTAGBUSY
Read
’0’ Used to indicate that a JTAG DRP transaction is in progress.
22
JTAG
MODIFIED
Read
Used to indicate that a write to DRP through the JTAG interface has
’0’
occurred. This bit is cleared when a successful DRP read/write operation
through the FPGA logic is performed. The DRP read/write through FPGA
logic fails, if JTAGLOCKED = ’1’
23
JTAG
LOCKED
Read
’0’
Used to indicate that a DRP port lock request has been made by the Joint
Test Action Group (JTAG) interface.
24 BUSY
Read
N/A ADC busy signal. This signal transitions high during an ADC conversion.
25 EOS
Read
End of Sequence. This signal transitions to an active High when the
N/A
measurement data from the last channel in the auto sequence is written to
the status registers. This bit is cleared when a read operation is performed
on status register.
26 EOC
Read
End of Conversion signal. This signal transitions to an active High at the end
N/A
of an ADC conversion when the measurement is written to the SYSMON
hard macro’s status register. This bit is cleared when a read operation is
performed on status register.
27 - 31 CHANNEL
[4 : 0]
Read
Channel selection outputs. The ADC input MUX channel selection for the
N/A current ADC conversion is placed on these outputs at the end of an ADC
conversion.
DS620 October 19, 2011
www.xilinx.com
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Product Specification