DS620 Datasheet, PDF (5/30 Pages) Dallas Semiconductor – Low-Voltage, +-0.5°C Accuracy Digital Thermometer and Thermostat

LogiCORE IP XPS SYSMON ADC (v3.00.b)
Structurally, the XPS SYSMON ADC IP Core consists of the SYSMON hard macro, the PLB Interface Module,
Optional Interrupt Source Controller Module, Soft Reset Module, SYSMON Reset Register, and additional logic to
interface to the core. The Soft Reset Module provides a way for resetting the entire IP without disturbing the entire
system. The SYSMON Reset Register is provided to reset the SYSMON hard macro only.
All read and write operations to the configuration and limit registers are synchronized to DCLK (the DCLK input
of SYSMON hard macro is connected to SPLB_Clk). The SYSMON hard macro has an internal clock divider which
divides DCLK by any integer ranging from 2 to 255 to generate ADCCLK, which is an internal clock used by the ADC.
Because an internal clock divider is provided, the DCLK frequency can be in the range of 2 MHz to 200 MHz in the
case of Virtex-5 devices and 2 MHz to 80 MHz in the case of Virtex-6 devices. See the Virtex-5 and Virtex-6 FPGA
data sheets for the maximum operating frequency of the XPS SYSMON ADC core.
The SYSMON hard macro operates either in event-driven or continuous-sampling mode. In event-driven sampling
mode, the conversion process is initiated on the rising edge of CONVST. The XPS SYSMON ADC core supports this
operation by providing a rising-edge signal on the external CONVST port or by writing into the CONVST Register.
In continuous sampling mode, the ADC continues to carry out a conversion on the selected analog inputs as long as
the ADCCLK (DCLK) is present. For more information on the SYSMON hard macro, see the System Monitor user
guide mentioned in Reference Documents section.
Design Parameters
To allow the user to obtain an XPS SYSMON ADC IP core that is uniquely tailored for the system, certain features
can be parameterized in the XPS SYSMON ADC design. This allows the user to configure a design that utilizes the
resources required by the system only and that operates with the best possible performance. The features that can
be parameterized are shown in Table 1.
Table 1: XPS SYSMON ADC Design Parameters
Generic Feature/Description
Parameter Name
Allowable Values
Default
Value
VHDL
Type
System Parameters
G1 Target FPGA family
C_FAMILY
virtex5, virtex6
virtex5
string
PLB Parameters
G2 PLB base address
C_BASEADDR
Valid Address⁽¹⁾
None⁽²⁾
std_logic_
vector
G3 PLB high address
C_HIGHADDR
Valid Address⁽¹⁾
None⁽²⁾
std_logic_
vector
G4
PLB least significant
address bus width
C_SPLB_AWIDTH
32
32
integer
G5 PLB data width
C_SPLB_DWIDTH
32, 64, 128
32
integer
G6 Shared bus topology C_SPLB_P2P
0 = Shared bus
topology⁽³⁾
0
integer
G7 PLB master ID bus Width C_SPLB_MID_WIDTH
log₂(C_SPLB_NUM_
MASTERS) with a
minimum value of 1
1
integer
G8 Number of PLB masters C_SPLB_NUM_MASTERS
1 - 16
1
integer
G9
Width of the slave data
bus
C_SPLB_NATIVE_DWIDTH
G10 Burst support
C_SPLB_SUPPORT_BURSTS
32
0 = No burst support⁽⁴⁾
32
integer
0
integer
XPS SYSMON ADC Parameters
DS620 October 19, 2011
www.xilinx.com
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Product Specification