DS620 Datasheet, PDF (23/30 Pages) Dallas Semiconductor – Low-Voltage, +-0.5°C Accuracy Digital Thermometer and Thermostat

LogiCORE IP XPS SYSMON ADC (v3.00.b)
Design Implementation
Target Technology
The intended target technology is Virtex-5 and Virtex-6 FPGAs.
Device Utilization and Performance Benchmarks
Core Performance
Because the XPS SYSMON ADC IP core can be used with other design modules in the FPGA, the utilization and
timing numbers reported in this section are estimates only. When the XPS SYSMON ADC IP core is combined with
other designs in the system, the utilization of FPGA resources and timing of the XPS SYSMON ADC IP core design
varies from the results reported here.
The XPS SYSMON ADC IP core resource utilization for various parameter combinations measured with the
Virtex-5 FPGA as the target device are detailed in Table 13.
Table 13: Performance and Resource Utilization Benchmarks on the Virtex-5 FPGA (xc5vlx50-ff676-1)
Parameter Values
(Other parameters at default values)
Device Resources
Performance
C_INCLUDE_INTR
0
Slice Flip-Flops
189
LUTs
114
F_Max (MHz)
150
1
Note:
251
139
150
1. For utilization calculation, the C_DCLK_RATIO = 1 is used, while the clock was targeted at 150 MHz.
The XPS SYSMON ADC IP core resource utilization for various parameter combinations measured with the
Virtex-6 FPGA as the target device are detailed in Table 14.
Table 14: Performance and Resource Utilization Benchmarks on the Virtex-6 FPGA (xc6vlx130t-ff1156-1)
Parameter Values (Other parameters at default values)
Device Resources
Performance
C_INCLUDE_INTR
0
Slice Flip-Flops
190
LUTs
149
F_Max (MHz)
200
1
Note:
252
236
200
1. For utilization calculation, the C_DCLK_RATIO = 3 is used, while the clock was targeted at 200 MHz.
System Performance
To measure the system performance (F_MAX) of the XPS SYSMON ADC core, it was added to a Virtex-5 and Virtex-6
FPGA system as the Device Under Test (DUT) as shown in Figure 16.
DS620 October 19, 2011
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Product Specification