DS620 Datasheet, PDF (24/30 Pages) Dallas Semiconductor – Low-Voltage, +-0.5°C Accuracy Digital Thermometer and Thermostat

X-Ref Target - Figure 16
LogiCORE IP XPS SYSMON ADC (v3.00.b)
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Figure 16: Virtex-5 and Virtex-6 FPGA System with the XPS SYSMON ADC Core as the DUT
The target FPGA was then filled with logic to drive the Lookup Table (LUT) and block Random Access Memory
(RAM) utilization to approximately 70% and the I/O utilization to approximately 80%. Using the default tool
options and the slowest speed grade for the target FPGA, the resulting target F_MAX numbers are shown in Table 15.
Table 15: XPS SYSMON ADC Core System Performance
Target FPGA
V5LXT50 -1
Target F_MAX (MHz)
120
V6LXT130-1
150
The target F_MAX is influenced by the exact system and is provided for guidance. It is not a guaranteed value across
all systems.
Precautions to be taken while Assigning the C_DCLK_RATIO Parameter
The C_DCLK_RATIO parameter has a range from 1 to 8. It is the user’s responsibility to set a particular value for
this parameter. The value set for this parameter divides the clock and the output of this division is provided to the
DCLK input of the SYSMON hard macro. This clock is provided through regional clocking nets. It is recommended
that the DCLK clock should be always set to 80 MHz with respect to the clock input to the core as well as the proper
C_DCLK_RATIO parameter. The user can set a different value for C_DCLK_RATIO, based upon the requirements.
If the DCLK clock is very slow, then the SYSMON can take a longer time for conversion of any input including the
on-chip parameter and Over Temperature (OT). In such cases, the alarm interrupt for on-chip parameters or Over
Temperature (OT) can come early than the actual EOC signal. User should take this into account while writing the
application. Also there is no timeout counter involved in the core. So if the DCLK is operating at a very slow speed,
then the transactions from the interface may be in wait mode, until the core generates an acknowledge signal for the
current transaction. This can affect the overall system performance.
User Application Examples
This section provides examples on configuring XPS SYSMON ADC IP core in either continuous cycling of sequence
or single channel (continuous or event driven) mode. It is assumed that the user is aware with the XPS SYSMON
ADC IP core register description given in Table 4, page 9.
DS620 October 19, 2011
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Product Specification