DS620 Datasheet, PDF (6/30 Pages) Dallas Semiconductor – Low-Voltage, +-0.5°C Accuracy Digital Thermometer and Thermostat

LogiCORE IP XPS SYSMON ADC (v3.00.b)
Table 1: XPS SYSMON ADC Design Parameters (Cont’d)
Generic Feature/Description
Parameter Name
G11
Include/Exclude
interrupt support
C_INCLUDE_INTR
G12
File name for Analog
input stimuli
C_SIM_MONITOR_FILE
G13 DCLK clock division ratio C_DCLK_RATIO
Allowable Values
0 = Exclude interrupt
support
1 = Include interrupt
support
string
1,2,3,4,5,6,7,8⁽⁵⁾
Default
Value
VHDL
Type
1
integer
Design.
txt
1⁽⁶⁾
string
string
Notes:
1. The range C_BASEADDR to C_HIGHADDR is the address range for the XPS SYSMON ADC core.This range is subject to
restrictions to accommodate the simple address decoding scheme that is employed: The size, C_HIGHADDR - C_BASEADDR +
1, must be a power of two and must be at least 0x400 to accommodate all XPS SYSMON ADC core registers. However, a larger
power of two can be chosen to reduce decoding logic. C_BASEADDR must be aligned to a multiple of the range size.
2. No default value is specified to ensure that an actual value appropriate to the system is set.
3. Point-to-point bus topology is not supported.
4. Burst is not supported.
5. Based upon the core frequency, this parameter should be set to generate the DCLK frequency less than or equal to 80 MHz. The
C_DCLK_RATIO supports a range of values between 1 to 8. Internally, this value is used to divide the clock. It is strongly
recommended that, the value of C_DCLK_RATIO should be set in such a way that, the DCLK input frequency to the SYSMON
macro is always equal to 80 MHz or close to 80 MHz. If the value chosen for C_DCLK_RATIO causes the DCLK to operate at very
low value, then the SYSMON macro takes a longer time to generate the DRDY signal and can hamper the core functionality and
efficiency while working with the interconnect. See Precautions to be taken while Assigning the C_DCLK_RATIO Parameter,
page 24 before using this parameter.
6. This parameter is set to 1 as default for all Virtex-5 devices. For all Virtex-6 devices this parameter needs to be assigned some
value. For Virtex-6 devices, the value of 1 is allowed when the core frequency is not exceeding the 80 MHz limit.
I/O Signals
The XPS SYSMON ADC Input/Output (I/O) signals are listed and described in Table 2.
Table 2: I/O Signal Descriptions
Port
Signal Name
Interface I/O
Initial
State
Description
System Signals
P1 SPLB_Clk
System
I
-
PLB clock
P2 SPLB_Rst
System
I
-
PLB reset, active high
P3 IP2INTC_Irpt
System
O
0
Interrupt control signal from XPS
SYSMON ADC
PLB Interface Signals
P4 PLB_ABus[0 : 31]
PLB
I
-
PLB address bus
P5 PLB_PAValid
PLB
I
-
PLB primary address valid
P6 PLB_masterID[0 : C_SPLB_MID_WIDTH - 1]
PLB
I
-
PLB current master identifier
P7 PLB_RNW
PLB
I
-
PLB read not write
P8 PLB_BE[0 : (C_SPLB_DWIDTH/8) - 1]
PLB
I
-
PLB byte enables
P9 PLB_size[0 : 3]
PLB
I
-
PLB size of requested transfer
P10 PLB_type[0 : 2]
PLB
I
-
PLB transfer type
P11 PLB_wrDBus[0 : C_SPLB_DWIDTH - 1]
PLB
I
-
PLB write data bus
DS620 October 19, 2011
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Product Specification