DS620 Datasheet, PDF (20/30 Pages) Dallas Semiconductor – Low-Voltage, +-0.5°C Accuracy Digital Thermometer and Thermostat

LogiCORE IP XPS SYSMON ADC (v3.00.b)
More about Locally Generated Interrupt Bits in IPIER and IPISR
The interrupt bits ranging from the bit-24 to bit-31 in the IPISR and IPIER registers are direct output signals of the
SYSMON hard macro. Signals such as OT Deactive (bit-23) and ALM[0] Deactive (bit-22) are locally generated in
the core. These two interrupts are generated on the falling edge of the Over Temperature and AML[0] signals. The
falling edge of these two signals can be used to control external functions, such as controlling the fan or
air-conditioning of the system. See the Virtex-5 FPGA System Monitor user guide (UG192) for detailed reference
about the significance of these interrupts.
SYSMON Hard Macro Register Grouping
The SYSMON hard macro register set consists of all the registers present in the SYSMON hard macro on Virtex-5
and Virtex-6 FPGAs. The addresses of these registers are mentioned in Table 4. Because these registers are 16-bit
wide, but the processor data bus is 32-bit wide, the hard macro register data resides on the lower 16 bits of the 32-bit
data bus as shown in Figure 11. The 10-bit MSB aligned A/D converted value of different channels from the
SYSMON hard macro is left shifted and resides from bit position 16 to 25 of the processor data bus. The remaining
bit positions from 26 to 31 should be ignored while considering the ADC data for different channels. Along with
16-bit data, the JTAGMODIFIED and JTAGLOCKED bits are passed, which can be used by the software driver
application for determining the validity of the DRP read data. The JTAGMODIFIED bit is cleared when a DRP
read/write operation through the FPGA logic is successful. A DRP read/write through the FPGA logic fails, if
JTAGLOCKED = ’1’. The JTAGLOCKED signal is independently controlled through JTAG TAP. It is expected that
these SYSMON hard macro registers should be accessed in their preferred access-mode only. The XPS SYSMON
ADC IP core will not be able to differentiate any non-preferred access to the SYSMON hard macro registers. For
more information on these registers, see the Reference Documents section.
X-Ref Target - Figure 11
Undefined
JTAG
MODIFIED
16-bit Hard
Macro Data
(DRP Data - Do)
0
13 14 15 16
31
JTAG
LOCKED
Figure 11: SYSMON Hard Macro Register
DS620_11_020509
DS620 October 19, 2011
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