DS567 Datasheet, PDF (8/24 Pages) Xilinx, Inc – This data sheet describes the DDR2 Memory Controller

DDR2 Memory Controller for PowerPC 440 Processors
Parameter - Port Dependencies
Table 4 illustrates the port and parameter dependencies. With the configuration flexibility of the
channelized access memory controller, the user must be aware of unused I/Os based on the
configuration of each port. The designer must also be aware of the external memory interface signals
based on the type of memory utilized in the system.
Table 4: Parameter-Port Dependencies
Name
Affects
Depends
Relationship Description
Design Parameters
C_NUM_CLK_PAIRS DDR_Clk, DDR_Clkn
Affects size of signals.
C_NUM_RANKS_MEM
DDR_CKE,
DDR_CSn,
DDR_ODT,
C_MEM_BASEADDR,
C_MEM_HIGHADDR
C_MEM_TYPE
Affects size of signals.
C_DDR_DWIDTH
DDR_DQ
Parameter affects size of DDR DQ
signals.
C_DDR_DQS_WIDTH DDR_DQS,
DDR_DQS_N
Parameter affects size of DDR DQS
signals.
C_DDR_DM_WIDTH DDR_DM
Parameter affects size of DDR DM
signals.
C_DDR_RAWIDTH
DDR_Addr
Affects size of signal.
C_DDR_BAWIDTH
DDR_BankAddr
Affects size of signal.
I/O Signals
DDR_Clk, DDR_Clkn
C_NUM_CLK_PAIRS Size depends on
C_NUM_CLK_PAIRS parameter.
DDR_CKE, DDR_CSn
C_NUM_RANKS_MEM Size depends on
C_NUM_RANKS_MEM parameter.
DDR_DQ
C_DDR_DWIDTH
Size depends on parameter setting.
DDR_DQS
C_DDR_DQS_WIDTH Size depends on parameter setting.
DDR_DM
C_DDR_DM_WIDTH Size depends on parameter setting.
DDR_Addr
C_DDR_RAWIDTH
Size depends on parameter setting.
DDR_BankAddr
C_DDR_BAWIDTH
Size depends on parameter setting.
DDR_DQS_N,
DDR_ODT
C_NUM_MEM_RANKS Size depends on parameter setting.
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DS567 (v1.1.1) March 31, 2008