DS567 Datasheet, PDF (3/24 Pages) Xilinx, Inc – This data sheet describes the DDR2 Memory Controller

DDR2 Memory Controller for PowerPC 440 Processors
Table 1: PPC440MC DDR2 Memory Controller I/O Signal Description (Cont’d)
Signal Name
Interface
Signal
Type
Initial
Status
Description
MIMCROWCONFLICT
MCI
I
This signal is asserted if the row being
accessed is different from the row
accessed in the previous command
MCMIREADDATA[0:127]
MCI
O
Read data bus
MCMIREADDATAVALID
MCI
O
When asserted, this signal indicates the
data on the read data bus is valid
MCMIREADDATAERR
MCI
O
This signal is asserted when an
uncorrectable error is detected by the
ECC logic.
MCMIADDRREADYTOACCEPT
MCI
O
This signal is asserted when the
PPC440MC DDR2 Memory Controller is
ready to accept transactions
DDR2 Signals
DDR2_DQ
(C_DDR_DWIDTH – 1:0)
DDR2 I/O
DDR2 data bus
DDR2_DQS
(C_DDR_DQS_WIDTH – 1:0)
DDR2 I/O
DDR2 data strobe
DDR2_DQS_N
(C_DDR_DQS_WIDTH – 1:0)
DDR2 I/O
DDR2 inverted data strobe
DDR2_A
(C_DDR_CAWIDTH – 1:0)
DDR2
O
DDR2 address
DDR2_BA
(C_DDR_BAWIDTH – 1:0)
DDR2
O
DDR2 bank address
DDR2_RAS_N
DDR2
O
DDR2 row address strobe
DDR2_CAS_N
DDR2
O
DDR2 column address strobe
DDR2_WE_N
DDR2
O
DDR2 write enable
DDR2_CS_N
DDR2
O
(C_NUM_RANKS_MEM – 1 down to 0)
DDR2 chip selects
DDR2_ODT
(C_DDR2_ODT_WIDTH – 1:0)
DDR2
O
DDR2 ODT enable signal
DDR2_CKE
DDR2
O
(C_DDR2_NUM_RANKS_MEM – 1:0)
DDR2 clock enable signal
DDR2_DM
(C_DDR_DM_WIDTH – 1:0)
DDR2
O
DDR2 data mask
DDR2_CK
(C_NUM_CLK_PAIRS – 1:0)
DDR2
O
DDR2 clock
DDR2_CK_N
(C_NUM_CLK_PAIRS – 1:0)
DDR2
O
DDR2 inverted clock
System Clock and Reset Signals
MI_MCCLK
CLK
I
Clock
MI_MCCLK90
CLK
I
Clock phase shifted by 90
MI_MCCLKDIV2
CLK
I
Clock divided by 2
MI_MCCLK_200
CLK
I
IDELAY reference clock
MI_MCRST
RST
I
Reset
DS567 (v1.1.1) March 31, 2008
www.xilinx.com
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