DS567 Datasheet, PDF (23/24 Pages) Xilinx, Inc – This data sheet describes the DDR2 Memory Controller

DDR2 Memory Controller for PowerPC 440 Processors
ECC Feature
The built in Hamming code error correction feature in the Virtex-5 FPGA block RAM using the
FIFO36_72 primitive supports the ECC feature in this memory controller. With this feature, double bit
errors can be detected and a single bit error can be corrected. The MCMIREADDATAERR signal
provides the double bit error status and should only be considered when the
C_INCLUDE_ECC_SUPPORT parameter is asserted. Single bit error status can be obtained from the
rd_ecc_err[1] signal in the mem_if_top.v module. The rd_ecc_err[1] signal is not provided to the MCI
interface. The ECC feature is only supported with 128-bit MCI data width and 72-bit external memory
interface width.
The MCI parameter MIB_RMW_ENABLE must be set to 1'b1 when the ECC feature in the memory
controller is enabled with the C_INCLUDE_ECC_SUPPORT parameter.
Read Modify Write
The computed ECC value for a write with partial byte enables will be incorrect because the disabled
bytes stored in the external memory location being accessed are not available during ECC calculation.
Therefore in case of writes with partial byte enables the controller must issue an additional read to re-
compute the ECC and write it back to the external memory device. When the memory controller detects
a write with partial byte enables, the MCMIADDRREADYTOACCEPT signal is deasserted in order to
prevent the MCI from issuing any more read or write command requests. The
MCMIADDRREADYTOACCEPT signal remains deasserted until the additional read command
(RMW_READ) followed by a write (RMW_WRITE) command have been executed by the memory
controller. The data read back by the RMW_READ command is modified with data to be written for
enabled bytes and stored in block RAM FIFOs (FIFO36_72) with the ECC feature turned ON. The
RMW_WRITE command simply reads the data to be written out of these FIFOs with the correct ECC
value. At the end of the RMW_WRITE transaction the MCMIADDRREADYTOACCEPT signal is
asserted.
Auto Hold Off and Write Data Delay Values in MCI
The controller is designed to work with an auto hold off value of 2 (four PPC440MC DDR2 Memory
Controller clocks) and a write data delay value of 0 (zero clocks). These values have to be set in the MCI
for optimal configuration.
Target Technology
The intended target technology is a Virtex-5 FXT FPGA.
Device Utilization and Performance Benchmarks
The HDL implementation modules automatically instantiate the necessary FPGA OBUF and IOBUF
resources for the DDR I/O signals.
To analyze the timing within the FPGA, the design has been implemented to illustrate the FPGA
performance and resource utilization values as shown in Table 9.
DS567 (v1.1.1) March 31, 2008
www.xilinx.com
23